diff --git a/.gitignore b/.gitignore index e7df822..9c77739 100644 --- a/.gitignore +++ b/.gitignore @@ -3,4 +3,7 @@ sdkconfig build __pycache__ *~ -sdkconfig.old \ No newline at end of file +sdkconfig.old +.config +*.bin +*.elf diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..85f48b2 --- /dev/null +++ b/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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+ struct bflb_device_s *gpio; + gpio = bflb_device_get_by_name("gpio"); +#ifdef CONFIG_PINMUX_ENABLE_LED1 + bflb_gpio_reset(gpio, BSP_GPIO_LED1); +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED2 + bflb_gpio_reset(gpio, BSP_GPIO_LED2); +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED3 + bflb_gpio_reset(gpio, BSP_GPIO_LED3); +#endif + bool led = false; while (1) { LOG_F("%s\r\n", CONFIG_EXAMPLE_HELLOWORLD); LOG_E("%s\r\n", CONFIG_EXAMPLE_HELLOWORLD); @@ -13,6 +26,32 @@ int main(void) LOG_I("%s\r\n", CONFIG_EXAMPLE_HELLOWORLD); LOG_D("%s\r\n", CONFIG_EXAMPLE_HELLOWORLD); LOG_T("%s\r\n", CONFIG_EXAMPLE_HELLOWORLD); +#ifdef CONFIG_PINMUX_ENABLE_LED1 + if (led == true) { + bflb_gpio_reset(gpio, BSP_GPIO_LED1); +#ifdef CONFIG_PINMUX_ENABLE_LED3 + bflb_gpio_set(gpio, BSP_GPIO_LED3); +#endif + led = false; + } else { +#ifdef CONFIG_PINMUX_ENABLE_LED3 + bflb_gpio_reset(gpio, BSP_GPIO_LED3); +#endif + bflb_gpio_set(gpio, BSP_GPIO_LED1); + led = true; + } +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN1 + bool led2 = false; + if (!bflb_gpio_read(gpio, BSP_GPIO_BTN1)) { + LOG_I("Button 1 is pressed\r\n"); + } +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN2 + if (!bflb_gpio_read(gpio, BSP_GPIO_BTN2)) { + LOG_I("Button 2 is pressed\r\n"); + } +#endif bflb_mtimer_delay_ms(CONFIG_EXAMPLE_INTERVAL); } } diff --git a/apps/m0_lowload/CMakeLists.txt b/apps/m0_lowload/CMakeLists.txt index 4413bbe..c6124bf 100644 --- a/apps/m0_lowload/CMakeLists.txt +++ b/apps/m0_lowload/CMakeLists.txt @@ -1,18 +1,16 @@ cmake_minimum_required(VERSION 3.15) -include(proj.conf) - # Get SDK path if(NOT SDK_PATH) get_filename_component(SDK_PATH ../../ ABSOLUTE) - if(EXISTS $ENV{MY_SDK_PATH}) - set(SDK_PATH $ENV{MY_SDK_PATH}) + if(EXISTS $ENV{OBLFR_SDK_PATH}) + set(SDK_PATH $ENV{OBLFR_SDK_PATH}) endif() endif() # Check SDK Path if(NOT EXISTS ${SDK_PATH}) - message(FATAL_ERROR "SDK path Error, Please set SDK_PATH or MY_SDK_PATH variable") + message(FATAL_ERROR "SDK path Error, Please set OBLFR_SDK_PATH variable") endif() include(${SDK_PATH}/cmake/bflbsdk.cmake) diff --git a/apps/m0_lowload/Makefile b/apps/m0_lowload/Makefile index 54db646..1886ae5 100644 --- a/apps/m0_lowload/Makefile +++ b/apps/m0_lowload/Makefile @@ -1,5 +1,7 @@ -PINE64_SDK_PATH := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))../../) +OBLFR_SDK_PATH := $(realpath $(dir $(realpath $(lastword $(MAKEFILE_LIST))))../../) + +-include sdkconfig CPU_ID = m0 -include $(PINE64_SDK_PATH)/cmake/project.build +include $(OBLFR_SDK_PATH)/cmake/project.build diff --git a/bsp/common/CMakeLists.txt b/bsp/common/CMakeLists.txt new file mode 100644 index 0000000..3b19ef7 --- /dev/null +++ b/bsp/common/CMakeLists.txt @@ -0,0 +1,4 @@ +sdk_add_include_directories(include) +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bsp_common.c) + +add_subdirectory(${SDK_PATH}/bsp/common/${CHIP} bsp_common_${CHIP}) diff --git a/bsp/common/Kconfig b/bsp/common/Kconfig new file mode 100644 index 0000000..00b810a --- /dev/null +++ b/bsp/common/Kconfig @@ -0,0 +1,60 @@ +osource "$(BFLB_BOARD_DIR)/$(BFLB_BOARD)/Kconfig" +osource "$(BFLB_BOARD_DIR)/common/$(BFLB_CHIP)/Kconfig" +comment "Generic BSP Config" +menuconfig JTAG_DEBUG + bool "JTAG debug support" + help + This option enables JTAG debug module and pins. + + if JTAG_DEBUG + if CHIP_BL808 + choice + prompt "CPU To attach JTAG Debug Socket to" + default JTAG_DEBUG_M0 + help + Select the core to attach the JTAG Debug Socket to. + config JTAG_DEBUG_M0 + bool "Debug M0 Core" + config JTAG_DEBUG_D0 + bool "Debug D0 Core" + config JTAG_DEBUG_LP + bool "Debug LP Core" + endchoice + endif + choice + prompt "JTAG Debug Pins" + default JTAG_DEBUG_PINS_GRP0 if BOARD_OX64 + default JTAG_DEBUG_PINS_GRP1 if BOARD_M1S_DOCK + help + Select the JTAG Debug Pins to use. + config JTAG_DEBUG_PINS_GRP0 + bool "JTAG Debug Pins Group 0" + help + JTAG Debug Pins are on: + - JTAG_TMS on GPIO6 + - JTAG_TDO on GPIO7 + - JTAG_TCK on GPIO12 + - JTAG_TDI on GPIO13 + This is the default debug header on the OX64 board + + config JTAG_DEBUG_PINS_GRP1 + bool "JTAG Debug Pins Group 1" + help + JTAG Debug Pins are on: + - JTAG_TMS on GPIO0 + - JTAG_TDO on GPIO1 + - JTAG_TCK on GPIO2 + - JTAG_TDI on GPIO3 + This configuration is used on the M1S Dock board + with the tf2jtag adapter board. + endchoice + endif +menu "Pinmux" + if BOARD_HAS_SDCARD + config PINMUX_ENABLE_SDH + bool "Enable SD Card Pinmux and Clock" + default y + help + Enable SD Card Pinmux and Clocks + endif +endmenu diff --git a/bsp/common/bl616/CMakeLists.txt b/bsp/common/bl616/CMakeLists.txt new file mode 100644 index 0000000..6f6e427 --- /dev/null +++ b/bsp/common/bl616/CMakeLists.txt @@ -0,0 +1,6 @@ +sdk_add_include_directories(include) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl616_bsp.c) + +sdk_set_linker_script(bl616_flash.ld) + diff --git a/bsp/common/bl616/Kconfig b/bsp/common/bl616/Kconfig new file mode 100644 index 0000000..f2e77b6 --- /dev/null +++ b/bsp/common/bl616/Kconfig @@ -0,0 +1,9 @@ +comment "BL616 SOC" + +config CHIP_BL616 + bool + default y if BFLB_CHIP_ID = "bl616" + +menu "BL616 CPU Config" +endmenu + diff --git a/bsp/ox64/mcu/bl808_flash_m0.ld b/bsp/common/bl616/bl616_flash.ld similarity index 75% rename from bsp/ox64/mcu/bl808_flash_m0.ld rename to bsp/common/bl616/bl616_flash.ld index 0e16e8c..8e81b9f 100644 --- a/bsp/ox64/mcu/bl808_flash_m0.ld +++ b/bsp/common/bl616/bl616_flash.ld @@ -17,41 +17,59 @@ INPUT(-lgcc) /* configure the entry point */ ENTRY(__start) -StackSize = 0x0400; /* 1KB */ +StackSize = 0x1000; /* 4KB */ HeapMinSize = 0x1000; /* 4KB */ +__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K; +__RFTLV_SIZE_OFFSET = 1K; +__RFTLV_SIZE_HOLE = 2K; +__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */ +__RFTLV_HEAD1_L = (0x41524150); /* PAPA */ + MEMORY { - fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K - fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K - dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K - ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K + fw_header_memory (rx) : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K + xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M + ram_code (wxa) : ORIGIN = 0xA8000000, LENGTH = 4M + itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K + dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K + nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K + ram_memory (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K + ram_wifi (wxa) : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE } SECTIONS { - .fw_header0 : - { - KEEP(*(.fw_header0)) - } > fw_header_memory0 - .fw_header1 : + BOOT2_PT_ADDR = 0x63027c00; + + .fw_header : { - KEEP(*(.fw_header1)) - } > fw_header_memory1 + KEEP(*(.fw_header)) + } > fw_header_memory + + .init : + { + *(.text.entry) + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + } > xip_memory + + .rftlv.tool : + { + . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET; + PROVIDE( _ld_symbol_rftlv_address = . ); + LONG(__RFTLV_HEAD1_H); + LONG(__RFTLV_HEAD1_L); + . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE; + } > xip_memory .text : { . = ALIGN(4); __text_code_start__ = .; - KEEP (*(SORT_NONE(.init))) - KEEP (*(SORT_NONE(.vector))) - *(.text) *(.text.*) @@ -74,20 +92,16 @@ SECTIONS __usbh_class_info_end__ = .; /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) + *(EXCLUDE_FILE( *bl616_glb*.o* \ + *bl616_pds*.o* \ + *bl616_common*.o* \ + *bl616_sf_cfg*.o* \ + *bl616_sf_ctrl*.o* \ + *bl616_sflash*.o* \ + *bl616_xip_sflash*.o* \ + *bl616_ef_ctrl*.o* \ + *bl616_romapi_patch*.o* ).rodata*) + *(.srodata) *(.srodata.*) @@ -108,20 +122,15 @@ SECTIONS *(.sclock_rlt_code.*) *(.sclock_rlt_const.*) - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) + *bl616_glb*.o*(.rodata*) + *bl616_pds*.o*(.rodata*) + *bl616_common*.o*(.rodata*) + *bl616_sf_cfg*.o*(.rodata*) + *bl616_sf_ctrl*.o*(.rodata*) + *bl616_sflash*.o*(.rodata*) + *bl616_xip_sflash*.o*(.rodata*) + *bl616_ef_ctrl*.o*(.rodata*) + *bl616_romapi_patch*.o*(.rodata*) . = ALIGN(4); __tcm_code_end__ = .; @@ -215,6 +224,10 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory diff --git a/bsp/common/bl616/include/bl616_bsp.h b/bsp/common/bl616/include/bl616_bsp.h new file mode 100644 index 0000000..7815b9a --- /dev/null +++ b/bsp/common/bl616/include/bl616_bsp.h @@ -0,0 +1,9 @@ +#ifndef BL616_BOARD_H +#define BL616_BOARD_H +#include +#include "bsp_common.h" +#include "sdkconfig.h" + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len); + +#endif \ No newline at end of file diff --git a/bsp/common/bl616/src/bl616_bsp.c b/bsp/common/bl616/src/bl616_bsp.c new file mode 100644 index 0000000..e09c292 --- /dev/null +++ b/bsp/common/bl616/src/bl616_bsp.c @@ -0,0 +1,213 @@ +#include "bflb_uart.h" +#include "bflb_gpio.h" +#include "bflb_clock.h" +#include "bflb_rtc.h" +#include "bflb_flash.h" +#include "bl616_bsp.h" +#include "bl616_tzc_sec.h" +#include "bl616_psram.h" +#include "bl616_glb.h" + +#include "mem.h" + +#define WB_4MB_PSRAM (1) + +#ifdef CONFIG_BSP_SDH_SDCARD +#include "sdh_sdcard.h" +#endif + +extern void log_start(void); + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static struct bflb_device_s *console; + + +static void system_clock_init(void) +{ +#if 1 + /* wifipll/audiopll */ + GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL); + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M); +#else + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); + GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL); + GLB_Config_AUDIO_PLL_To_384M(); + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1); + GLB_Set_MCU_System_CLK_Div(0, 3); +#endif + CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1); +} + +static void peripheral_clock_init(void) +{ + PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); + PERIPHERAL_CLOCK_SEC_ENABLE(); + PERIPHERAL_CLOCK_DMA0_ENABLE(); + PERIPHERAL_CLOCK_UART0_ENABLE(); + PERIPHERAL_CLOCK_UART1_ENABLE(); + PERIPHERAL_CLOCK_SPI0_ENABLE(); + PERIPHERAL_CLOCK_I2C0_ENABLE(); + PERIPHERAL_CLOCK_PWM0_ENABLE(); + PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); + PERIPHERAL_CLOCK_IR_ENABLE(); + PERIPHERAL_CLOCK_I2S_ENABLE(); + PERIPHERAL_CLOCK_USB_ENABLE(); + PERIPHERAL_CLOCK_CAN_ENABLE(); + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); + GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0); + GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0); + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); + GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK); + GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E); + GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19); + GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3); + + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); +#ifdef CONFIG_BSP_SDH_SDCARD + PERIPHERAL_CLOCK_SDH_ENABLE(); + GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_EXT_SDH); +#endif + + GLB_Set_USB_CLK_From_WIFIPLL(1); + GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0); +} + +static void bflb_init_psram_gpio(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + for (uint8_t i = 0; i < 12; i++) { + bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0); + } +} + +static void psram_winbond_default_init(void) +{ + PSRAM_Ctrl_Cfg_Type default_psram_ctrl_cfg = { + .vendor = PSRAM_CTRL_VENDOR_WINBOND, + .ioMode = PSRAM_CTRL_X8_MODE, + .size = PSRAM_SIZE_4MB, + .dqs_delay = 0xfff0, + }; + + PSRAM_Winbond_Cfg_Type default_winbond_cfg = { + .rst = DISABLE, + .clockType = PSRAM_CLOCK_DIFF, + .inputPowerDownMode = DISABLE, + .hybridSleepMode = DISABLE, + .linear_dis = ENABLE, + .PASR = PSRAM_PARTIAL_REFRESH_FULL, + .disDeepPowerDownMode = ENABLE, + .fixedLatency = DISABLE, + .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES, + .brustType = PSRAM_WRAPPED_BURST, + .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY, + .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, + }; + + PSram_Ctrl_Init(PSRAM0_ID, &default_psram_ctrl_cfg); + // PSram_Ctrl_Winbond_Reset(PSRAM0_ID); + PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &default_winbond_cfg); +} + +uint32_t board_psram_x8_init(void) +{ + uint16_t reg_read = 0; + + GLB_Set_PSRAMB_CLK_Sel(ENABLE, GLB_PSRAMB_EMI_WIFIPLL_320M, 0); + + bflb_init_psram_gpio(); + + /* psram init*/ + psram_winbond_default_init(); + /* check psram work or not */ + PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read); + return reg_read; +} + + +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +static void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_uart_init(gpio, GPIO_PIN_21, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_22, GPIO_UART_FUNC_UART0_RX); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 7; + cfg.rx_fifo_threshold = 7; + + console = bflb_device_get_by_name("uart0"); + + bflb_uart_init(console, &cfg); + bflb_uart_set_console(console); +} + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len) +{ + int ret = -1; + uintptr_t flag; + + flag = bflb_irq_save(); + + ret = bflb_flash_init(); + + system_clock_init(); + peripheral_clock_init(); + bflb_irq_initialize(); + + console_init(); + + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } + bl_show_flashinfo(); + + printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); + + printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1)); + printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); + printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + + log_start(); + + +#ifdef CONFIG_PSRAM + board_psram_x8_init(); + Tzc_Sec_PSRAMB_Access_Release(); +#endif + + bflb_irq_restore(flag); + board_common_setup_pinmux(pinmux_setup, len); + +} + + + + +#ifdef CONFIG_SHELL +#include "shell.h" + +static void reboot_cmd(int argc, char **argv) +{ + GLB_SW_POR_Reset(); +} +SHELL_CMD_EXPORT_ALIAS(reboot_cmd, reboot, reboot); +#endif diff --git a/bsp/common/bl702/CMakeLists.txt b/bsp/common/bl702/CMakeLists.txt new file mode 100644 index 0000000..2ce5871 --- /dev/null +++ b/bsp/common/bl702/CMakeLists.txt @@ -0,0 +1,6 @@ +sdk_add_include_directories(include) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl702_bsp.c) + +sdk_set_linker_script(bl702_flash.ld) + diff --git a/bsp/common/bl702/Kconfig b/bsp/common/bl702/Kconfig new file mode 100644 index 0000000..a095294 --- /dev/null +++ b/bsp/common/bl702/Kconfig @@ -0,0 +1,9 @@ +comment "BL702 SOC" + +config CHIP_BL708 + bool + default y if BFLB_CHIP_ID = "bl702" + +menu "BL702 CPU Config" +endmenu + diff --git a/bsp/ox64/bl808_flash_d0.ld b/bsp/common/bl702/bl702_flash.ld similarity index 58% rename from bsp/ox64/bl808_flash_d0.ld rename to bsp/common/bl702/bl702_flash.ld index c7077ff..5da6f39 100644 --- a/bsp/ox64/bl808_flash_d0.ld +++ b/bsp/common/bl702/bl702_flash.ld @@ -1,7 +1,7 @@ /**************************************************************************************** -* @file flash.ld +* @file bl702_flash.ld * -* @brief This file is the link script file (gnuarm or armgcc). +* @brief This file is the map file (gnuarm or armgcc). * * Copyright (C) BouffaloLab 2021 * @@ -11,27 +11,32 @@ /* configure the CPU type */ OUTPUT_ARCH( "riscv" ) /* link with the standard c library */ -INPUT(-lc) +/* INPUT(-lc) */ /* link with the standard GCC library */ -INPUT(-lgcc) +/* INPUT(-lgcc) */ /* configure the entry point */ ENTRY(__start) -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ +StackSize = 0x1000; /* 4KB */ MEMORY { - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K - dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K - xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K + fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K + itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 12K + dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K + ram_memory (!rx) : ORIGIN = 0x42018000, LENGTH = 96K + hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/ } SECTIONS { + PROVIDE(__metal_chicken_bit = 0); + + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory .text : { @@ -39,12 +44,13 @@ SECTIONS __text_code_start__ = .; KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) *(.text) *(.text.*) /* section information for shell */ - . = ALIGN(8); + . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) __fsymtab_end = .; @@ -55,20 +61,17 @@ SECTIONS __vsymtab_end = .; /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) + *(EXCLUDE_FILE( *bl702_glb*.o* \ + *bl702_pds*.o* \ + *bl702_common*.o* \ + *bl702_sf_cfg*.o* \ + *bl702_sf_cfg_ext*.o* \ + *bl702_sf_ctrl*.o* \ + *bl702_sflash*.o* \ + *bl702_sflash_ext*.o* \ + *bl702_xip_sflash*.o* \ + *bl702_xip_sflash_ext*.o* \ + *bl702_ef_ctrl*.o*) .rodata*) *(.srodata) *(.srodata.*) @@ -90,26 +93,36 @@ SECTIONS *(.sclock_rlt_code.*) *(.sclock_rlt_const.*) - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) + *bl702_glb*.o*(.rodata*) + *bl702_pds*.o*(.rodata*) + *bl702_common*.o*(.rodata*) + *bl702_sf_cfg*.o*(.rodata*) + *bl702_sf_cfg_ext*.o*(.rodata*) + *bl702_sf_ctrl*.o*(.rodata*) + *bl702_sflash*.o*(.rodata*) + *bl702_sflash_ext*.o*(.rodata*) + *bl702_xip_sflash*.o*(.rodata*) + *bl702_xip_sflash_ext*.o*(.rodata*) + *bl702_ef_ctrl*.o*(.rodata*) . = ALIGN(4); __tcm_code_end__ = .; } > itcm_memory - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .hbn_ram_region : AT (__hbn_load_addr) + { + . = ALIGN(4); + __hbn_ram_start__ = .; + *bl702_hbn_wakeup*.o*(.rodata*) + *(.hbn_ram_code*) + *(.hbn_ram_data) + . = ALIGN(4); + __hbn_ram_end__ = .; + } > hbn_memory + + __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region); .dtcm_region : AT (__dtcm_load_addr) { @@ -143,20 +156,8 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); .system_ram_data_region : AT (__system_ram_load_addr) { @@ -164,19 +165,12 @@ SECTIONS __system_ram_data_start__ = .; *(.system_ram) + *(.nocache_ram) . = ALIGN(4); __system_ram_data_end__ = .; } > ram_memory - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); /* Data section */ @@ -195,12 +189,13 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - .bss (NOLOAD) : { . = ALIGN(4); @@ -225,32 +220,21 @@ SECTIONS __noinit_data_end__ = .; } > ram_memory - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - .heap (NOLOAD): { . = ALIGN(4); __HeapBase = .; - /*__end__ = .;*/ - /*end = __end__;*/ KEEP(*(.heap*)) . = ALIGN(4); __HeapLimit = .; } > ram_memory + PROVIDE (__heap_min_size = 0x400); __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + + ASSERT((__HeapLimit - __HeapBase ) >= __heap_min_size, "heap size is too short.") } diff --git a/bsp/common/bl702/include/bl702_bsp.h b/bsp/common/bl702/include/bl702_bsp.h new file mode 100644 index 0000000..477729e --- /dev/null +++ b/bsp/common/bl702/include/bl702_bsp.h @@ -0,0 +1,9 @@ +#ifndef BL702_BSP_H +#define BL702_BSP_H +#include +#include "bsp_common.h" +#include "sdkconfig.h" + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len); + +#endif \ No newline at end of file diff --git a/bsp/common/bl702/src/bl702_bsp.c b/bsp/common/bl702/src/bl702_bsp.c new file mode 100644 index 0000000..28decbe --- /dev/null +++ b/bsp/common/bl702/src/bl702_bsp.c @@ -0,0 +1,220 @@ +#include "bflb_uart.h" +#include "bflb_gpio.h" +#include "bflb_clock.h" +#include "bflb_rtc.h" +#include "bflb_flash.h" +#include "bflb_spi_psram.h" +#include "bl702_glb.h" +#include "bl702_bsp.h" + +#include "mem.h" +#include "log.h" + +extern void log_start(void); + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static struct bflb_device_s *console; + +static void system_clock_init(void) +{ + GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL144M); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 71); +} + +static void peripheral_clock_init(void) +{ + PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); + PERIPHERAL_CLOCK_SEC_ENABLE(); + PERIPHERAL_CLOCK_DMA0_ENABLE(); + PERIPHERAL_CLOCK_UART0_ENABLE(); + PERIPHERAL_CLOCK_UART1_ENABLE(); + PERIPHERAL_CLOCK_SPI0_ENABLE(); + PERIPHERAL_CLOCK_I2C0_ENABLE(); + PERIPHERAL_CLOCK_PWM0_ENABLE(); + PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); + PERIPHERAL_CLOCK_IR_ENABLE(); + PERIPHERAL_CLOCK_I2S_ENABLE(); + PERIPHERAL_CLOCK_USB_ENABLE(); + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM); + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0); + GLB_Set_SPI_CLK(ENABLE, 0); + GLB_Set_I2C_CLK(ENABLE, 0); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 15); + + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); + GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E); + + GLB_Set_USB_CLK(ENABLE); +} + +/* bsp sf psram private variables */ + +struct spi_psram_cfg_type ap_memory1604 = { + .read_id_cmd = 0x9F, + .read_id_dmy_clk = 0, + .burst_toggle_cmd = 0xC0, + .reset_enable_cmd = 0x66, + .reset_cmd = 0x99, + .enter_quad_mode_cmd = 0x35, + .exit_quad_mode_cmd = 0xF5, + .read_reg_cmd = 0xB5, + .read_reg_dmy_clk = 1, + .write_reg_cmd = 0xB1, + .read_cmd = 0x03, + .read_dmy_clk = 0, + .f_read_cmd = 0x0B, + .f_read_dmy_clk = 1, + .f_read_quad_cmd = 0xEB, + .f_read_quad_dmy_clk = 3, + .write_cmd = 0x02, + .quad_write_cmd = 0x38, + .page_size = 512, + .ctrl_mode = PSRAM_SPI_CTRL_MODE, + .drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS, + .burst_length = PSRAM_BURST_LENGTH_512_BYTES, +}; + +struct sf_ctrl_cmds_cfg cmds_cfg = { + .cmds_core_en = 1, + .cmds_en = 1, + .burst_toggle_en = 1, + .cmds_wrap_mode = 0, + .cmds_wrap_len = SF_CTRL_WRAP_LEN_512, +}; +struct sf_ctrl_psram_cfg psram_cfg = { + .owner = SF_CTRL_OWNER_SAHB, + .pad_sel = SF_CTRL_SEL_DUAL_CS_SF2, + .bank_sel = SF_CTRL_SEL_PSRAM, + .psram_rx_clk_invert_src = 1, + .psram_rx_clk_invert_sel = 0, + .psram_delay_src = 1, + .psram_clk_delay = 1, +}; + +#define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25 +#define BFLB_EXTPSRAM_CLK_GPIO GLB_GPIO_PIN_27 +#define BFLB_EXTPSRAM_CS_GPIO GLB_GPIO_PIN_17 +#define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28 +#define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24 +#define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23 +#define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26 + +void ATTR_TCM_SECTION psram_gpio_init(void) +{ + GLB_GPIO_Cfg_Type cfg; + uint8_t gpiopins[7]; + uint8_t i = 0; + + cfg.gpioMode = GPIO_MODE_AF; + cfg.pullType = GPIO_PULL_UP; + cfg.drive = 3; + cfg.smtCtrl = 1; + cfg.gpioFun = GPIO_FUN_FLASH_PSRAM; + + gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO; + gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO; + gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO; + gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO; + gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO; + gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO; + gpiopins[6] = BFLB_EXTFLASH_CS_GPIO; + + for (i = 0; i < sizeof(gpiopins); i++) { + cfg.gpioPin = gpiopins[i]; + + if (i == 0 || i == 1 || i == 6) { + /*flash clk and cs is output*/ + cfg.gpioMode = GPIO_MODE_OUTPUT; + } else { + /*data are bidir*/ + cfg.gpioMode = GPIO_MODE_AF; + } + + GLB_GPIO_Init(&cfg); + } +} + +uint8_t psramId[8] = { 0 }; + +void ATTR_TCM_SECTION board_psram_init(void) +{ + psram_gpio_init(); + + bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg); + + bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode); + + bflb_psram_readid(&ap_memory1604, psramId); + bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE); + L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE); +} + + +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +static void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 15; + cfg.rx_fifo_threshold = 15; + + console = bflb_device_get_by_name("uart0"); + + bflb_uart_init(console, &cfg); + bflb_uart_set_console(console); +} + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len) +{ + int ret = -1; + uintptr_t flag; + + flag = bflb_irq_save(); + + ret = bflb_flash_init(); + + system_clock_init(); + peripheral_clock_init(); + bflb_irq_initialize(); + + console_init(); + + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + + log_start(); + + bl_show_log(); + if (ret != 0) { + LOG_E("flash init fail!!!\r\n"); + } + bl_show_flashinfo(); + + LOG_I("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); + + LOG_I("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + + +#ifdef CONFIG_PSRAM1 + board_psram_init(); +#endif + + bflb_irq_restore(flag); + board_common_setup_pinmux(pinmux_setup, len); + +} + diff --git a/bsp/common/bl808/CMakeLists.txt b/bsp/common/bl808/CMakeLists.txt new file mode 100644 index 0000000..90ec25f --- /dev/null +++ b/bsp/common/bl808/CMakeLists.txt @@ -0,0 +1,13 @@ +sdk_add_include_directories(include src) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_common.c) +if(CPU_ID STREQUAL "d0") +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_d0.c) +elseif(CPU_ID STREQUAL "m0") +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_m0.c) +else() +message(FATAL_ERROR "Unknown CPU") +endif() + +sdk_set_linker_script(bl808_flash_${CPU_ID}.ld) + diff --git a/bsp/common/bl808/Kconfig b/bsp/common/bl808/Kconfig new file mode 100644 index 0000000..2fe3375 --- /dev/null +++ b/bsp/common/bl808/Kconfig @@ -0,0 +1,35 @@ +comment "BL808 $(BFLB_CPU_ID) SOC" + +config CHIP_BL808 + bool + default y if BFLB_CHIP = "bl808" + +config CPU_M0 + bool + default y if BFLB_CPU_ID = "m0" +config CPU_D0 + bool + default y if BFLB_CPU_ID = "d0" +config CPU_LP + bool + default y if BFLB_CPU_ID = "lp" + + +menu "M0 CPU Config" + visible if CPU_M0 + menu "Pinmux" + if BOARD_HAS_SDCARD + config PINMUX_ENABLE_SDH + bool "Enable SD Card Pinmux and Clock" + default y + help + Enable SD Card Pinmux and Clocks + endif + endmenu +endmenu +menu "D0 CPU Config" + visible if CPU_D0 +endmenu +menu "LP CPU Config" + visible if CPU_LP +endmenu diff --git a/bsp/ox64/iot/bl808_flash_d0.ld b/bsp/common/bl808/bl808_flash_d0.ld similarity index 99% rename from bsp/ox64/iot/bl808_flash_d0.ld rename to bsp/common/bl808/bl808_flash_d0.ld index 5ef17d3..0cc5b61 100644 --- a/bsp/ox64/iot/bl808_flash_d0.ld +++ b/bsp/common/bl808/bl808_flash_d0.ld @@ -35,10 +35,9 @@ SECTIONS { .fw_header : { - KEEP(*(.fw_header)) + KEEP(*(.fw_header0)) } > fw_header_memory - .text : { . = ALIGN(4); diff --git a/bsp/ox64/iot/bl808_flash_m0.ld b/bsp/common/bl808/bl808_flash_m0.ld similarity index 95% rename from bsp/ox64/iot/bl808_flash_m0.ld rename to bsp/common/bl808/bl808_flash_m0.ld index 371d716..95965a2 100644 --- a/bsp/ox64/iot/bl808_flash_m0.ld +++ b/bsp/common/bl808/bl808_flash_m0.ld @@ -22,7 +22,8 @@ HeapMinSize = 0x1000; /* 4KB */ MEMORY { - fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K + fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K + fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K @@ -33,10 +34,15 @@ MEMORY SECTIONS { - .fw_header : + .fw_header0 : { - KEEP(*(.fw_header)) - } > fw_header_memory + KEEP(*(.fw_header0)) + } > fw_header_memory0 + + .fw_header1 : + { + KEEP(*(.fw_header1)) + } > fw_header_memory1 .text : { @@ -154,7 +160,9 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); .nocache_ram_region : AT (__nocache_ram_load_addr) diff --git a/bsp/common/bl808/include/bl808_bsp.h b/bsp/common/bl808/include/bl808_bsp.h new file mode 100644 index 0000000..1293799 --- /dev/null +++ b/bsp/common/bl808/include/bl808_bsp.h @@ -0,0 +1,11 @@ +#ifndef BL808_BOARD_H +#define BL808_BOARD_H +#include +#include "bsp_common.h" +#include "sdkconfig.h" + + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len); + + +#endif \ No newline at end of file diff --git a/bsp/common/bl808/src/bl808_bsp_common.c b/bsp/common/bl808/src/bl808_bsp_common.c new file mode 100644 index 0000000..de601c9 --- /dev/null +++ b/bsp/common/bl808/src/bl808_bsp_common.c @@ -0,0 +1,252 @@ +#include "bflb_uart.h" +#include "bflb_gpio.h" +#include "bflb_clock.h" +#include "bflb_rtc.h" +#include "bflb_flash.h" +#include "bl808_glb.h" +#include "bl808_psram_uhs.h" +#include "bl808_tzc_sec.h" +#include "bl808_ef_cfg.h" +#include "bl808_uhs_phy.h" +#include "mem.h" +#include "log.h" +#include "bl808_bsp_common.h" + + +#ifdef CONFIG_BSP_SDH_SDCARD +#include "sdh_sdcard.h" +#endif + + + +void board_common_init(pinmux_setup_t *pinmux_setup, uint32_t len) { + /* call to the init function in either bl808_d0.c or bl808_m0.c */ + bl808_cpu_init(); + board_common_setup_pinmux(pinmux_setup, len); +} + + +#if 0 +void board_uartx_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + bflb_gpio_uart_init(gpio, GPIO_PIN_4, GPIO_UART_FUNC_UART1_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_5, GPIO_UART_FUNC_UART1_RX); + bflb_gpio_uart_init(gpio, GPIO_PIN_6, GPIO_UART_FUNC_UART1_CTS); + bflb_gpio_uart_init(gpio, GPIO_PIN_7, GPIO_UART_FUNC_UART1_RTS); +} + +void board_i2c0_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* I2C0_SDA */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* I2C0_SCL */ + bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_spi0_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* spi cs */ + bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi miso */ + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi mosi */ + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi clk */ + bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_pwm_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_adc_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* ADC_CH0 */ + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH1 */ + bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH2 */ + bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH3 */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH4 */ + bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH5 */ + //bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH6 */ + bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH7 */ + bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH8 */ + bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH9 */ + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH10 */ + bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* ADC_CH11,note the FLASH pin */ + //bflb_gpio_init(gpio, GPIO_PIN_34, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); +} + +void board_dac_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* DAC_CHA */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* DAC_CHB */ + bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); +} + +void board_ir_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_0); + GLB_IR_RX_GPIO_Sel(GLB_GPIO_PIN_17); +} + +void board_emac_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + +#if defined(BL808) + // GLB_PER_Clock_UnGate(1<<12); +#endif +} + +void board_sdh_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); +} + +void board_dvp_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* I2C GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* Power down GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_reset(gpio, GPIO_PIN_21); + + /* Reset GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_set(gpio, GPIO_PIN_20); + + /* MCLK GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* DVP GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_csi_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V); +#if 1 /* sipeed m1s dock */ + /* I2C GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* MCLK GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* Power down GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_reset(gpio, GPIO_PIN_40); + + /* Reset GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_mtimer_delay_us(20); + bflb_gpio_set(gpio, GPIO_PIN_41); +#else + /* I2C GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* MCLK GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* Power down GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_reset(gpio, GPIO_PIN_6); + + /* Reset GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_mtimer_delay_us(20); + bflb_gpio_set(gpio, GPIO_PIN_23); +#endif +} + +void board_iso11898_gpio_init() +{ + // struct bflb_device_s *gpio; + + // gpio = bflb_device_get_by_name("gpio"); +} + +#endif diff --git a/bsp/common/bl808/src/bl808_bsp_common.h b/bsp/common/bl808/src/bl808_bsp_common.h new file mode 100644 index 0000000..55d4b5d --- /dev/null +++ b/bsp/common/bl808/src/bl808_bsp_common.h @@ -0,0 +1,10 @@ +#ifndef BL808_BSP_COMMON_H +#define BL808_BSP_COMMON_H +#include "sdkconfig.h" +#include "bl808_bsp.h" + +extern void log_start(void); + +void bl808_cpu_init(void); + +#endif \ No newline at end of file diff --git a/bsp/common/bl808/src/bl808_bsp_d0.c b/bsp/common/bl808/src/bl808_bsp_d0.c new file mode 100644 index 0000000..5f7d7ee --- /dev/null +++ b/bsp/common/bl808/src/bl808_bsp_d0.c @@ -0,0 +1,66 @@ +#include +//#include +//#include +//#include +//#include +//#include +#include +//#include +#include +#include "log.h" +#include + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static struct bflb_device_s *console; + +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +static void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 7; + cfg.rx_fifo_threshold = 7; + + console = bflb_device_get_by_name("uart3"); + + bflb_uart_init(console, &cfg); + bflb_uart_set_console(console); +} + + +void bl808_cpu_init(void) +{ + CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); + + bflb_irq_initialize(); + + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + + console_init(); + + log_start(); + + bl_show_log(); + + LOG_I("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); + +} + + + + diff --git a/bsp/common/bl808/src/bl808_bsp_m0.c b/bsp/common/bl808/src/bl808_bsp_m0.c new file mode 100644 index 0000000..614267f --- /dev/null +++ b/bsp/common/bl808/src/bl808_bsp_m0.c @@ -0,0 +1,223 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "log.h" +#include + + +static struct bflb_device_s *console; +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +void system_clock_init(void) +{ + /* wifipll/audiopll */ + GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | + GLB_PLL_CPUPLL | + GLB_PLL_UHSPLL | + GLB_PLL_MIPIPLL); + + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); + GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); + GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M); + + CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); +} + +void peripheral_clock_init(void) +{ + PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); + PERIPHERAL_CLOCK_SEC_ENABLE(); + PERIPHERAL_CLOCK_DMA0_ENABLE(); + PERIPHERAL_CLOCK_UART0_ENABLE(); + PERIPHERAL_CLOCK_UART1_ENABLE(); + PERIPHERAL_CLOCK_SPI0_1_ENABLE(); + PERIPHERAL_CLOCK_I2C0_ENABLE(); + PERIPHERAL_CLOCK_PWM0_ENABLE(); + PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); + PERIPHERAL_CLOCK_IR_ENABLE(); + PERIPHERAL_CLOCK_I2S_ENABLE(); + PERIPHERAL_CLOCK_USB_ENABLE(); + PERIPHERAL_CLOCK_CAN_UART2_ENABLE(); + + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4); + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); + GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0); + GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0); + GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19); + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); + GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK); + GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E); + GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END); + GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3); + + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); + +#ifdef CONFIG_BSP_CSI + GLB_CSI_Config_MIPIPLL(2, 0x21000); + GLB_CSI_Power_Up_MIPIPLL(); + GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1); +#endif + GLB_Set_USB_CLK_From_WIFIPLL(1); +} + +#ifdef CONFIG_PSRAM +#define WB_4MB_PSRAM (1) +#define UHS_32MB_PSRAM (2) +#define UHS_64MB_PSRAM (3) +#define WB_32MB_PSRAM (4) +#define NONE_UHS_PSRAM (-1) + +int uhs_psram_init(void) +{ + PSRAM_UHS_Cfg_Type psramDefaultCfg = { + 2000, + PSRAM_MEM_SIZE_32MB, + PSRAM_PAGE_SIZE_2KB, + PSRAM_UHS_NORMAL_TEMP, + }; + + bflb_efuse_device_info_type chip_info; + bflb_ef_ctrl_get_device_info(&chip_info); + if (chip_info.psramInfo == UHS_32MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB; + } else if (chip_info.psramInfo == UHS_64MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB; + } else { + return -1; + } + + //init uhs PLL; Must open uhs pll first, and then initialize uhs psram + GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); + //init uhs psram ; + // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000); + Psram_UHS_x16_Init_Override(&psramDefaultCfg); + Tzc_Sec_PSRAMA_Access_Release(); + + // example: 2000Mbps typical cal values + uhs_phy_cal_res->rl = 39; + uhs_phy_cal_res->rdqs = 3; + uhs_phy_cal_res->rdq = 0; + uhs_phy_cal_res->wl = 13; + uhs_phy_cal_res->wdqs = 4; + uhs_phy_cal_res->wdq = 5; + uhs_phy_cal_res->ck = 9; + /* TODO: use uhs psram trim update */ + set_uhs_latency_r(uhs_phy_cal_res->rl); + cfg_dqs_rx(uhs_phy_cal_res->rdqs); + cfg_dq_rx(uhs_phy_cal_res->rdq); + set_uhs_latency_w(uhs_phy_cal_res->wl); + cfg_dq_drv(uhs_phy_cal_res->wdq); + cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1); + cfg_dqs_drv(uhs_phy_cal_res->wdqs); + // set_odt_en(); + mr_read_back(); + return 0; +} +#endif + +void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 7; + cfg.rx_fifo_threshold = 7; + + console = bflb_device_get_by_name("uart0"); + bflb_uart_init(console, &cfg); + bflb_uart_set_console(console); +} + + +#if defined(CONFIG_PINMUX_ENABLE_SDH) +void enable_sdh_periheral() { + LOG_D("Enabling SD Card\r\n"); + PERIPHERAL_CLOCK_SDH_ENABLE(); + uint32_t tmp_val; + tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5); + uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN); + tmp_val2 &= ~(1 << 0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2); + BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); + GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH); + LOG_D("SDH peripheral clock: %d\r\n", bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_SDH, 0)/1000000); +} +#endif + +void bl808_cpu_init(void) +{ + int ret = -1; + uintptr_t flag; + + flag = bflb_irq_save(); + + GLB_Halt_CPU(GLB_CORE_ID_D0); + + ret = bflb_flash_init(); + + system_clock_init(); + peripheral_clock_init(); + bflb_irq_initialize(); + console_init(); +#if defined(CONFIG_PINMUX_ENABLE_SDH) + enable_sdh_periheral(); +#endif + + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + + log_start(); + + bl_show_log(); + if (ret != 0) { + LOG_E("flash init fail!!!\r\n"); + } + bl_show_flashinfo(); + + LOG_I("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); + + +#ifdef CONFIG_PSRAM + if (uhs_psram_init() < 0) { + while (1) { + } + } +#endif + /* set CPU D0 boot XIP address and flash address */ + // Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1); + // /* D0 boot from 0x58000000 */ + // GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000); + // /* D0 image offset on flash is 0x100000+0x1000(header) */ + // bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0); + + bflb_irq_restore(flag); + + /* we do not check header at 0x100000, just boot */ + GLB_Release_CPU(GLB_CORE_ID_D0); + + /* release d0 and then do can run */ + BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG); + BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG); + L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8); +} + + diff --git a/bsp/common/include/bsp_common.h b/bsp/common/include/bsp_common.h new file mode 100644 index 0000000..3b35bff --- /dev/null +++ b/bsp/common/include/bsp_common.h @@ -0,0 +1,128 @@ +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +typedef struct { + uint32_t pin; + uint32_t mode; + uint32_t pull; + uint32_t drive; + uint32_t func; +} pinmux_setup_t; + + +void bl_show_log(void); +void bl_show_flashinfo(void); +void board_common_setup_pinmux(pinmux_setup_t *pinmux_setup, uint32_t len); + +#if defined(CONFIG_JTAG_DEBUG) +#ifdef CONFIG_JTAG_DEBUG_PINS_GRP0 +#define JTAG_TMS_GPIOPIN GPIO_PIN_6 +#define JTAG_TDO_GPIOPIN GPIO_PIN_7 +#define JTAG_TCK_GPIOPIN GPIO_PIN_12 +#define JTAG_TDI_GPIOPIN GPIO_PIN_13 +#elif CONFIG_JTAG_DEBUG_PINS_GRP1 +#define JTAG_TMS_GPIOPIN GPIO_PIN_0 +#define JTAG_TDO_GPIOPIN GPIO_PIN_1 +#define JTAG_TCK_GPIOPIN GPIO_PIN_2 +#define JTAG_TDI_GPIOPIN GPIO_PIN_3 +#else +#error Unknown JTAG debug pins +#endif + +#ifdef CONFIG_BL808 +#ifdef CONFIG_JTAG_DEBUG_M0 +#define JTAG_GPIO_FUNC GPIO_FUNC_JTAG_M0 +#elif CONFIG_JTAG_DEBUG_D0 +#define JTAG_GPIO_FUNC GPIO_FUNC_JTAG_D0 +#elif CONFIG_JTAG_DEBUG_LP +#define JTAG_GPIO_FUNC GPIO_FUNC_JTAG_LP +#else +#error "Unknown CPU Selected for JTAG" +#endif +#elif defined(CONFIG_BL616) +#define JTAG_GPIO_FUNC GPIO_FUN_JTAG +#endif + +#endif + + +#ifdef CONFIG_PINMUX_ENABLE_SDH +#define PINMUX_ENABLE_SDH() \ + { \ + .pin = GPIO_PIN_0, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, \ + { \ + .pin = GPIO_PIN_1, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, \ + { \ + .pin = GPIO_PIN_2, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, \ + { \ + .pin = GPIO_PIN_3, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, \ + { \ + .pin = GPIO_PIN_4, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, \ + { \ + .pin = GPIO_PIN_5, \ + .mode = GPIO_ALTERNATE | GPIO_SMT_EN, \ + .pull = GPIO_PULLUP, \ + .drive = GPIO_DRV_2, \ + .func = GPIO_FUNC_SDH, \ + }, +#else +#define PINMUX_ENABLE_SDH() +#endif + +#ifdef CONFIG_JTAG_DEBUG +#define PINMUX_ENABLE_JTAG() \ + { \ + .pin = JTAG_TMS_GPIOPIN, \ + .mode = GPIO_ALTERNATE, \ + .func = JTAG_GPIO_FUNC, \ + }, \ + { \ + .pin = JTAG_TDO_GPIOPIN, \ + .mode = GPIO_ALTERNATE, \ + .func = JTAG_GPIO_FUNC, \ + }, \ + { \ + .pin = JTAG_TCK_GPIOPIN, \ + .mode = GPIO_ALTERNATE, \ + .func = JTAG_GPIO_FUNC, \ + }, \ + { \ + .pin = JTAG_TDI_GPIOPIN, \ + .mode = GPIO_ALTERNATE, \ + .func = JTAG_GPIO_FUNC, \ + }, +#else +#define PINMUX_ENABLE_JTAG() +#endif + +#define COMMON_PINMUX_SETUP() \ + PINMUX_ENABLE_SDH() \ + PINMUX_ENABLE_JTAG() + + +#endif \ No newline at end of file diff --git a/bsp/common/src/bsp_common.c b/bsp/common/src/bsp_common.c new file mode 100644 index 0000000..86a2382 --- /dev/null +++ b/bsp/common/src/bsp_common.c @@ -0,0 +1,129 @@ +#include +#include +#include +#include "bsp_common.h" +#include "log.h" + + +#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) +static struct bflb_device_s *rtc; +#endif + +void bl_show_log(void) +{ + LOG_I("\r\n"); + LOG_I(" ____ ____ __ __ _ \r\n"); + LOG_I(" / __ \\ | _ \\ / _|/ _| | | \r\n"); + LOG_I("| | | |_ __ ___ _ __ | |_) | ___ _ _| |_| |_ __ _| | ___ \r\n"); + LOG_I("| | | | '_ \\ / _ \\ '_ \\| _ < / _ \\| | | | _| _/ _` | |/ _ \\ \r\n"); + LOG_I("| |__| | |_) | __/ | | | |_) | (_) | |_| | | | || (_| | | (_) |\r\n"); + LOG_I(" \\____/| .__/ \\___|_| |_|____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/ \r\n"); + LOG_I(" | | \r\n"); + LOG_I(" |_| \r\n"); + LOG_I("\r\n"); + LOG_I("Powered by BouffaloLab\r\n"); + LOG_I("Build:%s,%s\r\n", __TIME__, __DATE__); + LOG_I("Copyright (c) 2023 OpenBouffalo team\r\n"); + LOG_I("Copyright (c) 2022 Bouffalolab team\r\n"); +} + +void bl_show_flashinfo(void) +{ + spi_flash_cfg_type flashCfg; + uint8_t *pFlashCfg = NULL; + uint32_t flashCfgLen = 0; + uint32_t flashJedecId = 0; + + flashJedecId = bflb_flash_get_jedec_id(); + bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen); + arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen); + LOG_I("=========== flash cfg ==============\r\n"); + LOG_I("jedec id 0x%06X\r\n", flashJedecId); + LOG_I("mid 0x%02X\r\n", flashCfg.mid); + LOG_I("iomode 0x%02X\r\n", flashCfg.io_mode); + LOG_I("clk delay 0x%02X\r\n", flashCfg.clk_delay); + LOG_I("clk invert 0x%02X\r\n", flashCfg.clk_invert); + LOG_I("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + LOG_I("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + LOG_I("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + LOG_I("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + LOG_I("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + LOG_I("cread support 0x%02X\r\n", flashCfg.c_read_support); + LOG_I("cread code 0x%02X\r\n", flashCfg.c_read_mode); + LOG_I("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); + LOG_I("=====================================\r\n"); +} + +void board_common_setup_pinmux(pinmux_setup_t *pinmux_setup, uint32_t len) { + uint32_t i; + struct bflb_device_s *gpio; + +#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) + rtc = bflb_device_get_by_name("rtc"); +#endif + + gpio = bflb_device_get_by_name("gpio"); + + for (i = 0; i < len; i++) { + uint32_t cfg; + if (pinmux_setup[i].mode & GPIO_ALTERNATE) { + cfg = pinmux_setup[i].mode | pinmux_setup[i].pull | pinmux_setup[i].drive | pinmux_setup[i].func; + } else { + cfg = pinmux_setup[i].mode | pinmux_setup[i].pull | pinmux_setup[i].drive; + } + bflb_gpio_init(gpio, pinmux_setup[i].pin, cfg); + LOG_D("pinmux_setup[%d] pin:%d, cfg:0x%08x\r\n", i, pinmux_setup[i].pin, cfg); + } + return; +} + +#ifdef CONFIG_BFLOG +__attribute__((weak)) uint64_t bflog_clock(void) +{ + return bflb_mtimer_get_time_us(); +} + +__attribute__((weak)) uint32_t bflog_time(void) +{ + return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)); +} + +__attribute__((weak)) char *bflog_thread(void) +{ + return ""; +} +#endif + +#ifdef CONFIG_LUA +__attribute__((weak)) clock_t luaport_clock(void) +{ + return (clock_t)bflb_mtimer_get_time_us(); +} + +__attribute__((weak)) time_t luaport_time(time_t *seconds) +{ + time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)); + if (seconds != NULL) { + *seconds = t; + } + + return t; +} +#endif + +#ifdef CONFIG_FATFS +#include "bflb_timestamp.h" +__attribute__((weak)) uint32_t get_fattime(void) +{ + bflb_timestamp_t tm; + + bflb_timestamp_utc2time(BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)), &tm); + + return ((uint32_t)(tm.year - 1980) << 25) /* Year 2015 */ + | ((uint32_t)tm.mon << 21) /* Month 1 */ + | ((uint32_t)tm.mday << 16) /* Mday 1 */ + | ((uint32_t)tm.hour << 11) /* Hour 0 */ + | ((uint32_t)tm.min << 5) /* Min 0 */ + | ((uint32_t)tm.sec >> 1); /* Sec 0 */ +} +#endif \ No newline at end of file diff --git a/bsp/m0sdock/CMakeLists.txt b/bsp/m0sdock/CMakeLists.txt new file mode 100644 index 0000000..76c7578 --- /dev/null +++ b/bsp/m0sdock/CMakeLists.txt @@ -0,0 +1,6 @@ +sdk_add_include_directories(.) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) + + + diff --git a/bsp/m0sdock/Kconfig b/bsp/m0sdock/Kconfig new file mode 100644 index 0000000..87cc433 --- /dev/null +++ b/bsp/m0sdock/Kconfig @@ -0,0 +1,19 @@ +config BOARD_M0SDOCK + bool + default y if BFLB_BOARD = "m0sdock" + +comment "M0S Dock Options" + +menu "Pinmux Configuration" + config PINMUX_ENABLE_LED1 + bool "Enable LED1 Pinmux" + default y + help + Enable LED1 Pinmux + config PINMUX_ENABLE_LED2 + bool "Enable LED1 Pinmux" + default y + help + Enable LED1 Pinmux + +endmenu diff --git a/bsp/m0sdock/board.c b/bsp/m0sdock/board.c new file mode 100644 index 0000000..c1d55c8 --- /dev/null +++ b/bsp/m0sdock/board.c @@ -0,0 +1,31 @@ +#include +#include +#include "board.h" +#include "log.h" + + +pinmux_setup_t pinmux_setup[] = { + COMMON_PINMUX_SETUP() +#ifdef CONFIG_PINMUX_ENABLE_LED1 + { + .pin = BSP_GPIO_LED1, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLDOWN, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED2 + { + .pin = BSP_GPIO_LED2, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLDOWN, + .drive = GPIO_DRV_1, + }, +#endif +}; + + +void board_init() { + board_common_init(pinmux_setup, sizeof(pinmux_setup)/sizeof(pinmux_setup_t)); +} + diff --git a/bsp/m0sdock/board.h b/bsp/m0sdock/board.h new file mode 100644 index 0000000..985b7d1 --- /dev/null +++ b/bsp/m0sdock/board.h @@ -0,0 +1,16 @@ +#ifndef _BOARD_H +#define _BOARD_H + +#include "bl616_bsp.h" +#include "bsp_common.h" + +void board_init(void); + +#ifdef CONFIG_PINMUX_ENABLE_LED1 +#define BSP_GPIO_LED1 GPIO_PIN_27 +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED2 +#define BSP_GPIO_LED2 GPIO_PIN_28 +#endif + +#endif \ No newline at end of file diff --git a/bsp/m0sense/CMakeLists.txt b/bsp/m0sense/CMakeLists.txt new file mode 100644 index 0000000..76c7578 --- /dev/null +++ b/bsp/m0sense/CMakeLists.txt @@ -0,0 +1,6 @@ +sdk_add_include_directories(.) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) + + + diff --git a/bsp/m0sense/Kconfig b/bsp/m0sense/Kconfig new file mode 100644 index 0000000..c3b06da --- /dev/null +++ b/bsp/m0sense/Kconfig @@ -0,0 +1,28 @@ +config BOARD_M0SENSE + bool + default y if BFLB_BOARD = "m0sense" + +comment "M0Sense Options" + +menu "Pinmux Configuration" + config PINMUX_ENABLE_LED1 + bool "Enable LED1 Pinmux (Red)" + default y + help + Enable LED1 Pinmux + config PINMUX_ENABLE_LED2 + bool "Enable LED2 Pinmux (Green) - Currently Broken" + default n + help + Enable LED2 Pinmux. Currently Broken. Need to investigate. + config PINMUX_ENABLE_LED3 + bool "Enable LED3 Pinmux (Blue)" + default y + help + Enable LED3 Pinmux + config PINMUX_ENABLE_BTN1 + bool "Enable Boot Button" + default y + help + Enable Boot Button +endmenu diff --git a/bsp/m0sense/board.c b/bsp/m0sense/board.c new file mode 100644 index 0000000..9f44765 --- /dev/null +++ b/bsp/m0sense/board.c @@ -0,0 +1,48 @@ +#include +#include +#include "board.h" +#include "log.h" + + +pinmux_setup_t pinmux_setup[] = { + COMMON_PINMUX_SETUP() +#ifdef CONFIG_PINMUX_ENABLE_LED1 + { + .pin = BSP_GPIO_LED1, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED2 + { + .pin = BSP_GPIO_LED2, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED3 + { + .pin = BSP_GPIO_LED3, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN1 + { + .pin = BSP_GPIO_BTN1, + .mode = GPIO_INPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +}; + + +void board_init() { + board_common_init(pinmux_setup, sizeof(pinmux_setup)/sizeof(pinmux_setup_t)); + printf("board init done\r\n"); +} + diff --git a/bsp/m0sense/board.h b/bsp/m0sense/board.h new file mode 100644 index 0000000..e855170 --- /dev/null +++ b/bsp/m0sense/board.h @@ -0,0 +1,22 @@ +#ifndef _BOARD_H +#define _BOARD_H + +#include "bl702_bsp.h" +#include "bsp_common.h" + +void board_init(void); + +#ifdef CONFIG_PINMUX_ENABLE_LED1 +#define BSP_GPIO_LED1 GPIO_PIN_25 +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED2 +#define BSP_GPIO_LED2 GPIO_PIN_24 +#endif +#ifdef CONFIG_PINMUX_ENABLE_LED3 +#define BSP_GPIO_LED3 GPIO_PIN_23 +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN1 +#define BSP_GPIO_BTN1 GPIO_PIN_2 +#endif + +#endif \ No newline at end of file diff --git a/bsp/m1sdock/CMakeLists.txt b/bsp/m1sdock/CMakeLists.txt new file mode 100644 index 0000000..76c7578 --- /dev/null +++ b/bsp/m1sdock/CMakeLists.txt @@ -0,0 +1,6 @@ +sdk_add_include_directories(.) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) + + + diff --git a/bsp/m1sdock/Kconfig b/bsp/m1sdock/Kconfig new file mode 100644 index 0000000..88844d9 --- /dev/null +++ b/bsp/m1sdock/Kconfig @@ -0,0 +1,27 @@ +config BOARD_M1SDOCK + bool + default y if BFLB_BOARD = "m1sdock" + +config BOARD_HAS_SDCARD + bool + default y if BFLB_BOARD = "m1sdock" + +comment "M1S Dock Options" + +menu "Pinmux Configuration" + config PINMUX_ENABLE_BTN1 + bool "Enable Button1 Pinmux" + default y + help + Enable Button1 Pinmux + config PINMUX_ENABLE_BTN2 + bool "Enable Button2 Pinmux" + default y + help + Enable Button2 Pinmux + config PINMUX_ENABLE_LED1 + bool "Enable LED1 Pinmux" + default y + help + Enable LED1 Pinmux +endmenu \ No newline at end of file diff --git a/bsp/m1sdock/board.c b/bsp/m1sdock/board.c new file mode 100644 index 0000000..1e43e25 --- /dev/null +++ b/bsp/m1sdock/board.c @@ -0,0 +1,37 @@ +#include +#include +#include "board.h" +#include "log.h" + +pinmux_setup_t pinmux_setup[] = { + COMMON_PINMUX_SETUP() +#ifdef CONFIG_PINMUX_ENABLE_LED1 + { + .pin = BSP_GPIO_LED1, + .mode = GPIO_OUTPUT, + .pull = GPIO_PULLDOWN, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN1 + { + .pin = BSP_GPIO_BTN1, + .mode = GPIO_INPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN2 + { + .pin = BSP_GPIO_BTN2, + .mode = GPIO_INPUT, + .pull = GPIO_PULLUP, + .drive = GPIO_DRV_1, + }, +#endif +}; + +void board_init() { + board_common_init(pinmux_setup, sizeof(pinmux_setup)/sizeof(pinmux_setup_t)); +} + diff --git a/bsp/m1sdock/board.h b/bsp/m1sdock/board.h new file mode 100644 index 0000000..face44a --- /dev/null +++ b/bsp/m1sdock/board.h @@ -0,0 +1,20 @@ +#ifndef _BOARD_H +#define _BOARD_H + +#include "bl808_bsp.h" +#include "bflb_gpio.h" + +void board_init(void); + +#ifdef CONFIG_PINMUX_ENABLE_LED1 +#define BSP_GPIO_LED1 GPIO_PIN_8 +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN1 +#define BSP_GPIO_BTN1 GPIO_PIN_22 +#endif +#ifdef CONFIG_PINMUX_ENABLE_BTN2 +#define BSP_GPIO_BTN2 GPIO_PIN_23 +#endif + + +#endif \ No newline at end of file diff --git a/bsp/ox64/CMakeLists.txt b/bsp/ox64/CMakeLists.txt index b56a903..76c7578 100644 --- a/bsp/ox64/CMakeLists.txt +++ b/bsp/ox64/CMakeLists.txt @@ -2,17 +2,5 @@ sdk_add_include_directories(.) target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) -if(CONFIG_IOT) -# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/iot/fw_header.c) -sdk_set_linker_script(iot/bl808_flash_${CPU_ID}.ld) -# sdk_add_link_options(-ufw_header) -else() -# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/mcu/fw_header.c) -sdk_set_linker_script(mcu/bl808_flash_${CPU_ID}.ld) -# sdk_add_link_options(-ufw_header0) -# sdk_add_link_options(-ufw_header1) -endif() -if(CONFIG_PSRAM) -sdk_add_compile_definitions(-DCONFIG_PSRAM) -endif() \ No newline at end of file + diff --git a/bsp/ox64/Kconfig b/bsp/ox64/Kconfig index 5510d6d..ea6c74c 100644 --- a/bsp/ox64/Kconfig +++ b/bsp/ox64/Kconfig @@ -1,20 +1,11 @@ -config JTAG_DEBUG - bool "JTAG debug support" - help - This option enables JTAG debug support for the test kernel. +config BOARD_OX64 + bool + default y if BFLB_BOARD = "ox64" + +config BOARD_HAS_SDCARD + bool + default y if BFLB_BOARD = "ox64" + +comment "ox64 Options" + -menu "JTAG Configuration" - visible if JTAG_DEBUG - choice - prompt "JTAG Pinmux" - default JTAG_M0 - help - Select the core to attach the JTAG Debug Socket to. - config JTAG_M0 - bool "Debug M0 Core" - config JTAG_D0 - bool "Debug D0 Core" - config JTAG_LP - bool "Debug LP Core" - endchoice -endmenu diff --git a/bsp/ox64/bl808_flash_m0.ld b/bsp/ox64/bl808_flash_m0.ld deleted file mode 100644 index 3b5cfc9..0000000 --- a/bsp/ox64/bl808_flash_m0.ld +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(__start) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K - dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K - ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(.init))) - KEEP (*(SORT_NONE(.vector))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb usbh_class_info */ - . = ALIGN(4); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - . = ALIGN(4); - __usbh_class_info_end__ = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_noinit_ram_data_start__ = .; - - *(.nocache_noinit_ram) - *(.noncacheable) - - . = ALIGN(4); - __nocache_noinit_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/ox64/board.c b/bsp/ox64/board.c index 846b9f1..a92f2e0 100644 --- a/bsp/ox64/board.c +++ b/bsp/ox64/board.c @@ -1,579 +1,16 @@ -#include "bflb_uart.h" -#include "bflb_gpio.h" -#include "bflb_clock.h" -#include "bflb_rtc.h" -#include "bflb_flash.h" -#include "bl808_glb.h" -#include "bl808_psram_uhs.h" -#include "bl808_tzc_sec.h" -#include "bl808_ef_cfg.h" -#include "bl808_uhs_phy.h" -#include "board.h" +#include +#include +#include "bl808_bsp.h" +#include "log.h" -#include "mem.h" -#ifdef CONFIG_BSP_SDH_SDCARD -#include "sdh_sdcard.h" -#endif +pinmux_setup_t pinmux_setup[] = { + COMMON_PINMUX_SETUP() +}; -extern void log_start(void); -extern uint32_t __HeapBase; -extern uint32_t __HeapLimit; +void board_init() { + board_common_init(pinmux_setup, sizeof(pinmux_setup)/sizeof(pinmux_setup_t)); -static struct bflb_device_s *uart0; - -#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) -static struct bflb_device_s *rtc; -#endif - -#if defined(CPU_M0) -static void system_clock_init(void) -{ - /* wifipll/audiopll */ - GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | - GLB_PLL_CPUPLL | - GLB_PLL_UHSPLL | - GLB_PLL_MIPIPLL); - - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); - GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M); - - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); } -static void peripheral_clock_init(void) -{ - PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); - PERIPHERAL_CLOCK_SEC_ENABLE(); - PERIPHERAL_CLOCK_DMA0_ENABLE(); - PERIPHERAL_CLOCK_UART0_ENABLE(); - PERIPHERAL_CLOCK_UART1_ENABLE(); - PERIPHERAL_CLOCK_SPI0_1_ENABLE(); - PERIPHERAL_CLOCK_I2C0_ENABLE(); - PERIPHERAL_CLOCK_PWM0_ENABLE(); - PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); - PERIPHERAL_CLOCK_IR_ENABLE(); - PERIPHERAL_CLOCK_I2S_ENABLE(); - PERIPHERAL_CLOCK_USB_ENABLE(); - PERIPHERAL_CLOCK_CAN_UART2_ENABLE(); - - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4); - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0); - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0); - GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0); - GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19); - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1); - GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK); - GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E); - GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END); - GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3); - - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); - -#ifdef CONFIG_BSP_SDH_SDCARD - PERIPHERAL_CLOCK_SDH_ENABLE(); - uint32_t tmp_val; - tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5); - uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN); - tmp_val2 &= ~(1 << 0); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2); - BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH); -#endif -#ifdef CONFIG_BSP_CSI - GLB_CSI_Config_MIPIPLL(2, 0x21000); - GLB_CSI_Power_Up_MIPIPLL(); - GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1); -#endif - GLB_Set_USB_CLK_From_WIFIPLL(1); -} - -#ifdef CONFIG_PSRAM -#define WB_4MB_PSRAM (1) -#define UHS_32MB_PSRAM (2) -#define UHS_64MB_PSRAM (3) -#define WB_32MB_PSRAM (4) -#define NONE_UHS_PSRAM (-1) - -int uhs_psram_init(void) -{ - PSRAM_UHS_Cfg_Type psramDefaultCfg = { - 2000, - PSRAM_MEM_SIZE_32MB, - PSRAM_PAGE_SIZE_2KB, - PSRAM_UHS_NORMAL_TEMP, - }; - - bflb_efuse_device_info_type chip_info; - bflb_ef_ctrl_get_device_info(&chip_info); - if (chip_info.psramInfo == UHS_32MB_PSRAM) { - psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB; - } else if (chip_info.psramInfo == UHS_64MB_PSRAM) { - psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB; - } else { - return -1; - } - - //init uhs PLL; Must open uhs pll first, and then initialize uhs psram - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - //init uhs psram ; - // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000); - Psram_UHS_x16_Init_Override(&psramDefaultCfg); - Tzc_Sec_PSRAMA_Access_Release(); - - // example: 2000Mbps typical cal values - uhs_phy_cal_res->rl = 39; - uhs_phy_cal_res->rdqs = 3; - uhs_phy_cal_res->rdq = 0; - uhs_phy_cal_res->wl = 13; - uhs_phy_cal_res->wdqs = 4; - uhs_phy_cal_res->wdq = 5; - uhs_phy_cal_res->ck = 9; - /* TODO: use uhs psram trim update */ - set_uhs_latency_r(uhs_phy_cal_res->rl); - cfg_dqs_rx(uhs_phy_cal_res->rdqs); - cfg_dq_rx(uhs_phy_cal_res->rdq); - set_uhs_latency_w(uhs_phy_cal_res->wl); - cfg_dq_drv(uhs_phy_cal_res->wdq); - cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1); - cfg_dqs_drv(uhs_phy_cal_res->wdqs); - // set_odt_en(); - mr_read_back(); - return 0; -} -#endif -#endif - -void bl_show_log(void) -{ - printf("\r\n"); - printf(" ____ __ __ _ _ _ \r\n"); - printf(" | _ \\ / _|/ _| | | | | | | \r\n"); - printf(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); - printf(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); - printf(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); - printf(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); - printf("\r\n"); - printf("Build:%s,%s\r\n", __TIME__, __DATE__); - printf("Copyright (c) 2022 Bouffalolab team\r\n"); -} - -void bl_show_flashinfo(void) -{ - spi_flash_cfg_type flashCfg; - uint8_t *pFlashCfg = NULL; - uint32_t flashCfgLen = 0; - uint32_t flashJedecId = 0; - - flashJedecId = bflb_flash_get_jedec_id(); - bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen); - arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen); - printf("=========== flash cfg ==============\r\n"); - printf("jedec id 0x%06X\r\n", flashJedecId); - printf("mid 0x%02X\r\n", flashCfg.mid); - printf("iomode 0x%02X\r\n", flashCfg.io_mode); - printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); - printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); - printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); - printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); - printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); - printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); - printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); - printf("cread support 0x%02X\r\n", flashCfg.c_read_support); - printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); - printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); - printf("=====================================\r\n"); -} - -extern void bflb_uart_set_console(struct bflb_device_s *dev); - -static void console_init() -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); -#if defined(CPU_M0) - bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); - bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); -#elif defined(CPU_D0) - /* sipeed m1s dock */ - bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); -#endif - struct bflb_uart_config_s cfg; - cfg.baudrate = 2000000; - cfg.data_bits = UART_DATA_BITS_8; - cfg.stop_bits = UART_STOP_BITS_1; - cfg.parity = UART_PARITY_NONE; - cfg.flow_ctrl = 0; - cfg.tx_fifo_threshold = 7; - cfg.rx_fifo_threshold = 7; -#if defined(CPU_M0) - uart0 = bflb_device_get_by_name("uart0"); -#elif defined(CPU_D0) - uart0 = bflb_device_get_by_name("uart3"); -#endif - bflb_uart_init(uart0, &cfg); - bflb_uart_set_console(uart0); -} - -#if defined(CPU_M0) -void board_init(void) -{ - int ret = -1; - uintptr_t flag; - - flag = bflb_irq_save(); - - ret = bflb_flash_init(); - - GLB_Halt_CPU(GLB_CORE_ID_D0); - - system_clock_init(); - peripheral_clock_init(); - bflb_irq_initialize(); - - console_init(); - - size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - kmem_init((void *)&__HeapBase, heap_len); - - bl_show_log(); - if (ret != 0) { - printf("flash init fail!!!\r\n"); - } - bl_show_flashinfo(); - - printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); - - printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1)); - printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); - - log_start(); - -#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) - rtc = bflb_device_get_by_name("rtc"); -#endif - -#ifdef CONFIG_PSRAM - if (uhs_psram_init() < 0) { - while (1) { - } - } -#endif - /* set CPU D0 boot XIP address and flash address */ - // Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1); - // /* D0 boot from 0x58000000 */ - // GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000); - // /* D0 image offset on flash is 0x100000+0x1000(header) */ - // bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0); - - bflb_irq_restore(flag); - - /* we do not check header at 0x10000, just boot */ - GLB_Release_CPU(GLB_CORE_ID_D0); - - /* release d0 and then do can run */ - BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG); - BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG); - L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8); -} -#elif defined(CPU_D0) -void board_init(void) -{ - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); - - bflb_irq_initialize(); - - size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - kmem_init((void *)&__HeapBase, heap_len); - - console_init(); - - bl_show_log(); - - printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); - - printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1)); - printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); - printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); - - log_start(); -} -#endif - -void board_uartx_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - - bflb_gpio_uart_init(gpio, GPIO_PIN_4, GPIO_UART_FUNC_UART1_TX); - bflb_gpio_uart_init(gpio, GPIO_PIN_5, GPIO_UART_FUNC_UART1_RX); - bflb_gpio_uart_init(gpio, GPIO_PIN_6, GPIO_UART_FUNC_UART1_CTS); - bflb_gpio_uart_init(gpio, GPIO_PIN_7, GPIO_UART_FUNC_UART1_RTS); -} - -void board_i2c0_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - /* I2C0_SDA */ - bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - /* I2C0_SCL */ - bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); -} - -void board_spi0_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - /* spi cs */ - bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - /* spi miso */ - bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - /* spi mosi */ - bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - /* spi clk */ - bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); -} - -void board_pwm_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLDOWN | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); -} - -void board_adc_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - /* ADC_CH0 */ - bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH1 */ - bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH2 */ - bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH3 */ - bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH4 */ - bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH5 */ - //bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH6 */ - bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH7 */ - bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH8 */ - bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH9 */ - bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH10 */ - bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* ADC_CH11,note the FLASH pin */ - //bflb_gpio_init(gpio, GPIO_PIN_34, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); -} - -void board_dac_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - /* DAC_CHA */ - bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - /* DAC_CHB */ - bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); -} - -void board_ir_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); - bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_0); - GLB_IR_RX_GPIO_Sel(GLB_GPIO_PIN_17); -} - -void board_emac_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_EMAC | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - -#if defined(BL808) - // GLB_PER_Clock_UnGate(1<<12); -#endif -} - -void board_sdh_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); - bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); - bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); - bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); - bflb_gpio_init(gpio, GPIO_PIN_4, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); - bflb_gpio_init(gpio, GPIO_PIN_5, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); -} - -void board_dvp_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - /* I2C GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* Power down GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_reset(gpio, GPIO_PIN_21); - - /* Reset GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_set(gpio, GPIO_PIN_20); - - /* MCLK GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* DVP GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_24, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_25, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_26, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_27, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_28, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_32, GPIO_FUNC_CAM | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); -} - -void board_csi_gpio_init(void) -{ - struct bflb_device_s *gpio; - - gpio = bflb_device_get_by_name("gpio"); - - GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V); -#if 1 /* sipeed m1s dock */ - /* I2C GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* MCLK GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* Power down GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_reset(gpio, GPIO_PIN_40); - - /* Reset GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_mtimer_delay_us(20); - bflb_gpio_set(gpio, GPIO_PIN_41); -#else - /* I2C GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* MCLK GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* Power down GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_reset(gpio, GPIO_PIN_6); - - /* Reset GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_mtimer_delay_us(20); - bflb_gpio_set(gpio, GPIO_PIN_23); -#endif -} - -void board_iso11898_gpio_init() -{ - // struct bflb_device_s *gpio; - - // gpio = bflb_device_get_by_name("gpio"); -} - -#ifdef CONFIG_BFLOG -__attribute__((weak)) uint64_t bflog_clock(void) -{ - return bflb_mtimer_get_time_us(); -} - -__attribute__((weak)) uint32_t bflog_time(void) -{ - return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)); -} - -__attribute__((weak)) char *bflog_thread(void) -{ - return ""; -} -#endif - -#ifdef CONFIG_LUA -__attribute__((weak)) clock_t luaport_clock(void) -{ - return (clock_t)bflb_mtimer_get_time_us(); -} - -__attribute__((weak)) time_t luaport_time(time_t *seconds) -{ - time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)); - if (seconds != NULL) { - *seconds = t; - } - - return t; -} -#endif - -#ifdef CONFIG_FATFS -#include "bflb_timestamp.h" -__attribute__((weak)) uint32_t get_fattime(void) -{ - bflb_timestamp_t tm; - - bflb_timestamp_utc2time(BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)), &tm); - - return ((uint32_t)(tm.year - 1980) << 25) /* Year 2015 */ - | ((uint32_t)tm.mon << 21) /* Month 1 */ - | ((uint32_t)tm.mday << 16) /* Mday 1 */ - | ((uint32_t)tm.hour << 11) /* Hour 0 */ - | ((uint32_t)tm.min << 5) /* Min 0 */ - | ((uint32_t)tm.sec >> 1); /* Sec 0 */ -} -#endif diff --git a/bsp/ox64/board.h b/bsp/ox64/board.h index ca7b074..9ec6c8b 100644 --- a/bsp/ox64/board.h +++ b/bsp/ox64/board.h @@ -1,26 +1,8 @@ #ifndef _BOARD_H #define _BOARD_H +#include "bl808_bsp.h" + void board_init(void); -void board_jtag_gpio_init(void); -void board_uartx_gpio_init(void); -void board_i2c0_gpio_init(void); -void board_spi0_gpio_init(void); -void board_pwm_gpio_init(void); -void board_adc_gpio_init(void); -void board_dac_gpio_init(void); -void board_ir_gpio_init(void); -void board_emac_gpio_init(void); -void board_sdh_gpio_init(void); -void board_dvp_gpio_init(void); -void board_csi_gpio_init(void); -void board_iso11898_gpio_init(void); - -#define DEFAULT_TEST_UART "uart1" -#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX -#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX -#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR -#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR - #endif \ No newline at end of file diff --git a/bsp/ox64/iot/fw_header.c b/bsp/ox64/iot/fw_header.c deleted file mode 100644 index 833d99d..0000000 --- a/bsp/ox64/iot/fw_header.c +++ /dev/null @@ -1,199 +0,0 @@ -#include "fw_header.h" - -__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { - .magiccode = 0x504e4642, - .rivison = 0x00000001, - /*flash config */ - .flash_cfg.magiccode = 0x47464346, - .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ - .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ - .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ - .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ - .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ - .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ - .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ - .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ - .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ - .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ - .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ - .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ - .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ - .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ - .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ - .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ - .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ - .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ - .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ - .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ - .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ - .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ - .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ - .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ - .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ - .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ - .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ - .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ - .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ - .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ - .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ - .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ - .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ - .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ - .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ - .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ - .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ - .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ - .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ - .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ - .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ - .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ - .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ - .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ - .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ - .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ - .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ - .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ - .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ - .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ - .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ - .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ - .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ - .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ - .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ - .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ - .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ - .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ - .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ - .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ - .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ - .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ - .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ - .flash_cfg.cfg.qeData = 0, /*!< QE set data */ - .flash_cfg.crc32 = 0xdeadbeef, - /* clock cfg */ - .clk_cfg.magiccode = 0x47464350, - .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ - .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ - .clk_cfg.cfg.mcu_clk_div = 0x00, - .clk_cfg.cfg.mcu_bclk_div = 0x00, - - .clk_cfg.cfg.mcu_pbclk_div = 0x03, - .clk_cfg.cfg.lp_div = 0x01, - .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ - .clk_cfg.cfg.dsp_clk_div = 0x00, - - .clk_cfg.cfg.dsp_bclk_div = 0x01, - .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ - .clk_cfg.cfg.dsp_pbclk_div = 0x00, - .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ - - .clk_cfg.cfg.emi_clk_div = 0x01, - .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ - .clk_cfg.cfg.flash_clk_div = 0x00, - .clk_cfg.cfg.wifipll_pu = 0x01, - - .clk_cfg.cfg.aupll_pu = 0x01, - .clk_cfg.cfg.cpupll_pu = 0x01, - .clk_cfg.cfg.mipipll_pu = 0x01, - .clk_cfg.cfg.uhspll_pu = 0x01, - - .clk_cfg.crc32 = 0xdeadbeef, - - /* basic cfg */ - .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ - .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ - .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ - .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ - .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ - .basic_cfg.no_segment = 0x1, /* [8] no segment info */ - .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ - .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ - .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ - .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ - .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ - .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ - .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ - .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ - .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ -#if 0 -# 0 : cmds bypass wrap commands to macro, original mode; -# 1 : cmds handle wrap commands, original mode; -# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; -# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 -#endif - .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ -#if 0 -# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, -# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 -#endif - .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ - .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ - .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ - .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ - - .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */ - .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ - - .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */ - .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ - - /* cpu cfg */ - .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */ - .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].rsvd = 0x0, - - .cpu_cfg[0].cache_range_h = 0x00000000, - .cpu_cfg[0].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[0].image_address_offset = 0x0, - .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ - - /* cpu cfg */ - .cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */ - .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].rsvd = 0x0, - - .cpu_cfg[1].cache_range_h = 0x00000000, - .cpu_cfg[1].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[1].image_address_offset = 0x0, - .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ - - /* address of partition table 0 */ /* 4 */ - .boot2_pt_table_0_rsvd = 0x00000000, - /* address of partition table 1 */ /* 4 */ - .boot2_pt_table_1_rsvd = 0x00000000, - - /* address of flashcfg table list */ /* 4 */ - .flash_cfg_table_addr = 0x00000000, - /* flashcfg table list len */ /* 4 */ - .flash_cfg_table_len = 0x00000000, - - .crc32 = 0xdeadbeef /* 4 */ -}; diff --git a/bsp/ox64/iot/fw_header.h b/bsp/ox64/iot/fw_header.h deleted file mode 100644 index f9dbc39..0000000 --- a/bsp/ox64/iot/fw_header.h +++ /dev/null @@ -1,210 +0,0 @@ -#ifndef __FW_HEADER_H__ -#define __FW_HEADER_H__ - -#include "stdint.h" -#include "stdio.h" - -struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ - uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -}; - -struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { - uint32_t magiccode; - struct spi_flash_cfg_t cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { - uint8_t xtal_type; - uint8_t mcu_clk; - uint8_t mcu_clk_div; - uint8_t mcu_bclk_div; - - uint8_t mcu_pbclk_div; - uint8_t lp_div; - uint8_t dsp_clk; - uint8_t dsp_clk_div; - - uint8_t dsp_bclk_div; - uint8_t dsp_pbclk; - uint8_t dsp_pbclk_div; - uint8_t emi_clk; - - uint8_t emi_clk_div; - uint8_t flash_clk_type; - uint8_t flash_clk_div; - uint8_t wifipll_pu; - - uint8_t aupll_pu; - uint8_t cpupll_pu; - uint8_t mipipll_pu; - uint8_t uhspll_pu; -}; - -struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { - uint32_t magiccode; - struct sys_clk_cfg_t cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { - uint32_t sign_type : 2; /* [1: 0] for sign */ - uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ - uint32_t key_sel : 2; /* [5: 4] key slot */ - uint32_t xts_mode : 1; /* [6] for xts mode */ - uint32_t aes_region_lock : 1; /* [7] rsvd */ - uint32_t no_segment : 1; /* [8] no segment info */ - uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ - uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ - uint32_t cpu_master_id : 4; /* [14: 11] master id */ - uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ - uint32_t crc_ignore : 1; /* [16] ignore crc */ - uint32_t hash_ignore : 1; /* [17] hash ignore */ - uint32_t power_on_mm : 1; /* [18] power on mm */ - uint32_t em_sel : 3; /* [21: 19] em_sel */ - uint32_t cmds_en : 1; /* [22] command spliter enable */ - uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ - uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ - uint32_t icache_invalid : 1; /* [29] icache invalid */ - uint32_t dcache_invalid : 1; /* [30] dcache invalid */ - uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ - - uint32_t group_image_offset; /* flash controller offset */ - uint32_t aes_region_len; /* aes region length */ - - uint32_t img_len_cnt; /* image length or segment count */ - uint32_t hash[32 / 4]; /* hash of the image */ -}; - -struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { - uint8_t config_enable; /* coinfig this cpu */ - uint8_t halt_cpu; /* halt this cpu */ - uint8_t cache_enable : 1; /* cache setting */ - uint8_t cache_wa : 1; /* cache setting */ - uint8_t cache_wb : 1; /* cache setting */ - uint8_t cache_wt : 1; /* cache setting */ - uint8_t cache_way_dis : 4; /* cache setting */ - uint8_t rsvd; - - uint32_t cache_range_h; /* cache range high */ - uint32_t cache_range_l; /* cache range low */ - - uint32_t image_address_offset; /* image_address_offset */ - uint32_t rsvd0; /* rsvd0 */ - uint32_t msp_val; /* msp value */ -}; - -struct __attribute__((packed, aligned(4))) aesiv_cfg_t { - uint8_t aesiv[16]; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) pkey_cfg_t { - uint8_t eckeyx[32]; /* ec key in boot header */ - uint8_t eckeyy[32]; /* ec key in boot header */ - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) sign_cfg_t { - uint32_t sig_len; - uint8_t signature[32]; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) bootheader_t { - uint32_t magiccode; /* 4 */ - uint32_t rivison; /* 4 */ - - struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ - struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */ - - struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ - - struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */ - - uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ - uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ - - uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ - uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ - - uint32_t rsvd0[6]; /* rsvd */ - uint32_t rsvd1[6]; /* rsvd */ - - uint32_t rsvd3[5]; /* 4 */ - - uint32_t crc32; /* 4 */ -}; - -#endif \ No newline at end of file diff --git a/bsp/ox64/mcu/bl808_flash_d0.ld b/bsp/ox64/mcu/bl808_flash_d0.ld deleted file mode 100644 index f527e25..0000000 --- a/bsp/ox64/mcu/bl808_flash_d0.ld +++ /dev/null @@ -1,261 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(__start) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K - dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K - xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K -} - -SECTIONS -{ - .fw_header : - { - KEEP(*(.fw_header0)) - } > fw_header_memory - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(.init))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(8); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/ox64/mcu/fw_header.c b/bsp/ox64/mcu/fw_header.c deleted file mode 100644 index 3a788bc..0000000 --- a/bsp/ox64/mcu/fw_header.c +++ /dev/null @@ -1,403 +0,0 @@ -#include "fw_header.h" - -__attribute__((section(".fw_header0"))) struct bootheader_t fw_header0 = { - .magiccode = 0x504e4642, - .rivison = 0x00000001, - /*flash config */ - .flash_cfg.magiccode = 0x47464346, - .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ - .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ - .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ - .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ - .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ - .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ - .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ - .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ - .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ - .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ - .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ - .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ - .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ - .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ - .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ - .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ - .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ - .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ - .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ - .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ - .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ - .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ - .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ - .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ - .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ - .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ - .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ - .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ - .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ - .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ - .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ - .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ - .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ - .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ - .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ - .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ - .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ - .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ - .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ - .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ - .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ - .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ - .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ - .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ - .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ - .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ - .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ - .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ - .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ - .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ - .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ - .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ - .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ - .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ - .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ - .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ - .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ - .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ - .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ - .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ - .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ - .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ - .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ - .flash_cfg.cfg.qeData = 0, /*!< QE set data */ - .flash_cfg.crc32 = 0xdeadbeef, - /* clock cfg */ - .clk_cfg.magiccode = 0x47464350, - .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ - .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ - .clk_cfg.cfg.mcu_clk_div = 0x00, - .clk_cfg.cfg.mcu_bclk_div = 0x00, - - .clk_cfg.cfg.mcu_pbclk_div = 0x03, - .clk_cfg.cfg.lp_div = 0x01, - .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ - .clk_cfg.cfg.dsp_clk_div = 0x00, - - .clk_cfg.cfg.dsp_bclk_div = 0x01, - .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ - .clk_cfg.cfg.dsp_pbclk_div = 0x00, - .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ - - .clk_cfg.cfg.emi_clk_div = 0x01, - .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ - .clk_cfg.cfg.flash_clk_div = 0x00, - .clk_cfg.cfg.wifipll_pu = 0x01, - - .clk_cfg.cfg.aupll_pu = 0x01, - .clk_cfg.cfg.cpupll_pu = 0x01, - .clk_cfg.cfg.mipipll_pu = 0x01, - .clk_cfg.cfg.uhspll_pu = 0x01, - - .clk_cfg.crc32 = 0xdeadbeef, - - /* basic cfg */ - .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ - .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ - .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ - .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ - .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ - .basic_cfg.no_segment = 0x1, /* [8] no segment info */ - .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ - .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ - .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ - .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ - .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ - .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ - .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ - .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ - .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ -#if 0 -# 0 : cmds bypass wrap commands to macro, original mode; -# 1 : cmds handle wrap commands, original mode; -# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; -# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 -#endif - .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ -#if 0 -# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, -# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 -#endif - .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ - .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ - .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ - .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ - - .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */ - .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ - - .basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */ - .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ - - /* cpu cfg */ - .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */ - .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].rsvd = 0x0, - - .cpu_cfg[0].cache_range_h = 0x00000000, - .cpu_cfg[0].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[0].image_address_offset = 0x0, - .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ - - /* cpu cfg */ - .cpu_cfg[1].config_enable = 0x00, /* coinfig this cpu */ - .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].rsvd = 0x0, - - .cpu_cfg[1].cache_range_h = 0x00000000, - .cpu_cfg[1].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[1].image_address_offset = 0x0, - .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ - - /* address of partition table 0 */ /* 4 */ - .boot2_pt_table_0_rsvd = 0x00000000, - /* address of partition table 1 */ /* 4 */ - .boot2_pt_table_1_rsvd = 0x00000000, - - /* address of flashcfg table list */ /* 4 */ - .flash_cfg_table_addr = 0x00000000, - /* flashcfg table list len */ /* 4 */ - .flash_cfg_table_len = 0x00000000, - - .rsvd1[0] = 0x20000320, - .rsvd1[1] = 0x00000000, - .rsvd1[2] = 0x2000F038, - .rsvd1[3] = 0x18000000, - - .crc32 = 0xdeadbeef /* 4 */ -}; - -__attribute__((section(".fw_header1"))) struct bootheader_t fw_header1 = { - .magiccode = 0x50414642, - .rivison = 0x00000001, - /*flash config */ - .flash_cfg.magiccode = 0x47464346, - .flash_cfg.cfg.ioMode = 0x10, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ - .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ - .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ - .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ - .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ - .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ - .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ - .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ - .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ - .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ - .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ - .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ - .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ - .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ - .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ - .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ - .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ - .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ - .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ - .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ - .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ - .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ - .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ - .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ - .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ - .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ - .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ - .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ - .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ - .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ - .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ - .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ - .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ - .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ - .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ - .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ - .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ - .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ - .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ - .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ - .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ - .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ - .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ - .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ - .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ - .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ - .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ - .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ - .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ - .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ - .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ - .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ - .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ - .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ - .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ - .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ - .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ - .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ - .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ - .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ - .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ - .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ - .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ - .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ - .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ - .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ - .flash_cfg.cfg.qeData = 0, /*!< QE set data */ - .flash_cfg.crc32 = 0xdeadbeef, - /* clock cfg */ - .clk_cfg.magiccode = 0x47464350, - .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ - .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ - .clk_cfg.cfg.mcu_clk_div = 0x00, - .clk_cfg.cfg.mcu_bclk_div = 0x00, - - .clk_cfg.cfg.mcu_pbclk_div = 0x03, - .clk_cfg.cfg.lp_div = 0x01, - .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ - .clk_cfg.cfg.dsp_clk_div = 0x00, - - .clk_cfg.cfg.dsp_bclk_div = 0x01, - .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ - .clk_cfg.cfg.dsp_pbclk_div = 0x00, - .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ - - .clk_cfg.cfg.emi_clk_div = 0x01, - .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ - .clk_cfg.cfg.flash_clk_div = 0x00, - .clk_cfg.cfg.wifipll_pu = 0x01, - - .clk_cfg.cfg.aupll_pu = 0x01, - .clk_cfg.cfg.cpupll_pu = 0x01, - .clk_cfg.cfg.mipipll_pu = 0x01, - .clk_cfg.cfg.uhspll_pu = 0x01, - - .clk_cfg.crc32 = 0xdeadbeef, - - /* basic cfg */ - .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ - .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ - .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ - .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ - .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ - .basic_cfg.no_segment = 0x1, /* [8] no segment info */ - .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ - .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ - .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ - .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ - .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ - .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ - .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ - .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ - .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ -#if 0 -# 0 : cmds bypass wrap commands to macro, original mode; -# 1 : cmds handle wrap commands, original mode; -# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; -# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 -#endif - .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ -#if 0 -# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, -# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 -#endif - .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ - .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ - .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ - .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ - - .basic_cfg.group_image_offset = 0x00011000, /* flash controller offset */ - .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ - - .basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */ - .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ - - /* cpu cfg */ - .cpu_cfg[0].config_enable = 0x00, /* coinfig this cpu */ - .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[0].rsvd = 0x0, - - .cpu_cfg[0].cache_range_h = 0x00000000, - .cpu_cfg[0].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[0].image_address_offset = 0x0, - - .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ - - /* cpu cfg */ - .cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */ - .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ - .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ - .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ - .cpu_cfg[1].rsvd = 0x0, - - .cpu_cfg[1].cache_range_h = 0x00000000, - .cpu_cfg[1].cache_range_l = 0x00000000, - /* image_address_offset */ - .cpu_cfg[1].image_address_offset = 0x0, - .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ - .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ - - /* address of partition table 0 */ /* 4 */ - .boot2_pt_table_0_rsvd = 0x00000000, - /* address of partition table 1 */ /* 4 */ - .boot2_pt_table_1_rsvd = 0x00000000, - - /* address of flashcfg table list */ /* 4 */ - .flash_cfg_table_addr = 0x00000000, - /* flashcfg table list len */ /* 4 */ - .flash_cfg_table_len = 0x00000000, - - .crc32 = 0xdeadbeef /* 4 */ -}; diff --git a/bsp/ox64/mcu/fw_header.h b/bsp/ox64/mcu/fw_header.h deleted file mode 100644 index f9dbc39..0000000 --- a/bsp/ox64/mcu/fw_header.h +++ /dev/null @@ -1,210 +0,0 @@ -#ifndef __FW_HEADER_H__ -#define __FW_HEADER_H__ - -#include "stdint.h" -#include "stdio.h" - -struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ - uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -}; - -struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { - uint32_t magiccode; - struct spi_flash_cfg_t cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { - uint8_t xtal_type; - uint8_t mcu_clk; - uint8_t mcu_clk_div; - uint8_t mcu_bclk_div; - - uint8_t mcu_pbclk_div; - uint8_t lp_div; - uint8_t dsp_clk; - uint8_t dsp_clk_div; - - uint8_t dsp_bclk_div; - uint8_t dsp_pbclk; - uint8_t dsp_pbclk_div; - uint8_t emi_clk; - - uint8_t emi_clk_div; - uint8_t flash_clk_type; - uint8_t flash_clk_div; - uint8_t wifipll_pu; - - uint8_t aupll_pu; - uint8_t cpupll_pu; - uint8_t mipipll_pu; - uint8_t uhspll_pu; -}; - -struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { - uint32_t magiccode; - struct sys_clk_cfg_t cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { - uint32_t sign_type : 2; /* [1: 0] for sign */ - uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ - uint32_t key_sel : 2; /* [5: 4] key slot */ - uint32_t xts_mode : 1; /* [6] for xts mode */ - uint32_t aes_region_lock : 1; /* [7] rsvd */ - uint32_t no_segment : 1; /* [8] no segment info */ - uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ - uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ - uint32_t cpu_master_id : 4; /* [14: 11] master id */ - uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ - uint32_t crc_ignore : 1; /* [16] ignore crc */ - uint32_t hash_ignore : 1; /* [17] hash ignore */ - uint32_t power_on_mm : 1; /* [18] power on mm */ - uint32_t em_sel : 3; /* [21: 19] em_sel */ - uint32_t cmds_en : 1; /* [22] command spliter enable */ - uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ - uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ - uint32_t icache_invalid : 1; /* [29] icache invalid */ - uint32_t dcache_invalid : 1; /* [30] dcache invalid */ - uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ - - uint32_t group_image_offset; /* flash controller offset */ - uint32_t aes_region_len; /* aes region length */ - - uint32_t img_len_cnt; /* image length or segment count */ - uint32_t hash[32 / 4]; /* hash of the image */ -}; - -struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { - uint8_t config_enable; /* coinfig this cpu */ - uint8_t halt_cpu; /* halt this cpu */ - uint8_t cache_enable : 1; /* cache setting */ - uint8_t cache_wa : 1; /* cache setting */ - uint8_t cache_wb : 1; /* cache setting */ - uint8_t cache_wt : 1; /* cache setting */ - uint8_t cache_way_dis : 4; /* cache setting */ - uint8_t rsvd; - - uint32_t cache_range_h; /* cache range high */ - uint32_t cache_range_l; /* cache range low */ - - uint32_t image_address_offset; /* image_address_offset */ - uint32_t rsvd0; /* rsvd0 */ - uint32_t msp_val; /* msp value */ -}; - -struct __attribute__((packed, aligned(4))) aesiv_cfg_t { - uint8_t aesiv[16]; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) pkey_cfg_t { - uint8_t eckeyx[32]; /* ec key in boot header */ - uint8_t eckeyy[32]; /* ec key in boot header */ - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) sign_cfg_t { - uint32_t sig_len; - uint8_t signature[32]; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) bootheader_t { - uint32_t magiccode; /* 4 */ - uint32_t rivison; /* 4 */ - - struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ - struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */ - - struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ - - struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */ - - uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ - uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ - - uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ - uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ - - uint32_t rsvd0[6]; /* rsvd */ - uint32_t rsvd1[6]; /* rsvd */ - - uint32_t rsvd3[5]; /* 4 */ - - uint32_t crc32; /* 4 */ -}; - -#endif \ No newline at end of file diff --git a/cmake.patch b/cmake.patch new file mode 100644 index 0000000..273e420 --- /dev/null +++ b/cmake.patch @@ -0,0 +1,30 @@ +diff --git a/cmake/bflbsdk.cmake b/cmake/bflbsdk.cmake +index 8b7ceb2..65265aa 100644 +--- a/cmake/bflbsdk.cmake ++++ b/cmake/bflbsdk.cmake +@@ -1,5 +1,7 @@ + cmake_minimum_required(VERSION 3.15) + ++include(proj.conf OPTIONAL RESULT_VARIABLE proj_conf_file) ++ + if(CONFIG_BFLB_BOARD) + set(BOARD ${CONFIG_BFLB_BOARD}) + endif() +@@ -10,6 +12,7 @@ if(CONFIG_BFLB_CPU_ID) + set(CPU_ID ${CONFIG_BFLB_CPU_ID}) + endif() + ++ + if(BOARD STREQUAL "ox64") + set(CHIP "bl808") + elseif(BOARD STREQUAL "m1sdock") +@@ -41,9 +44,6 @@ if(BOARD_DIR) + message(STATUS "BOARD_DIR: ${BOARD_DIR}") + endif() + +-include(proj.conf OPTIONAL RESULT_VARIABLE proj_conf_file) +- +- + find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + include(${SDK_PATH}/cmake/kconfig.cmake) + diff --git a/cmake/SDKconfig b/cmake/SDKconfig index fae4d75..5c48ba6 100644 --- a/cmake/SDKconfig +++ b/cmake/SDKconfig @@ -1,54 +1,65 @@ -mainmenu "Pine64 OX64 SDK configuration" +mainmenu "OpenBouffalo SDK configuration" +config BFLB_CHIP + string + default "$(BFLB_CHIP)" + +config BFLB_BOARD + string + default "$(BFLB_BOARD)" + +config BFLB_CPU_ID + string + default "$(BFLB_CPU_ID)" + +comment "Configuration for $(BFLB_CHIP) $(BFLB_CPU_ID) ($(BFLB_BOARD))" menu "Application" osource "Kconfig" endmenu menu "Board Support Configuration" - menu "$(BFLB_BOARD) Board Config" - source "$(BFLB_BOARD_DIR)/$(BFLB_BOARD)/Kconfig" - endmenu - + osource "$(BFLB_BOARD_DIR)/common/Kconfig" + config PSRAM bool "Enable PSRAM" default y config ETHERNET - bool "Enable Ethernet" + bool "Enable Ethernet SDK Driver" default n config BSP_SDH_SDCARD - bool "Enable SD SDHCI Driver Support" - default n - - config BSP_SPI_SDCARD - bool "Enable SD SPI Driver Support" + bool "Enable SD SDHCI SDK Driver" + depends on BOARD_HAS_SDCARD + select PINMUX_ENABLE_SDH default n config BSP_LCD - bool "Enable LCD Driver Support" + bool "Enable LCD SDK Driver" + default n + + config BSP_TOUCH + bool "Enable Touch SDK Driver" default n config BSP_IMAGE_SENSOR - bool "Enable Image Sensor Driver Support" + bool "Enable Image Sensor SDK" default n + + config BSP_CSI + bool "Enable CSI SDK Driver" + default n + depends on BSP_IMAGE_SENSOR + endmenu menu "CPU Configuration" - config BFLB_CHIP - string - default "$(BFLB_CHIP)" - config BLFB_CPU_ID - string - default "$(BFLB_CPU_ID)" - config ROMAPI bool "Enable ROM API" default y endmenu - menu "SDK configuration" menu "Logging Configuration" choice LOG_TYPE @@ -58,7 +69,6 @@ menu "SDK configuration" Select the logging type to use. config BFLOG bool "Use BFLOG Implementation" - depends on SDK_BROKEN config LOG bool "Use Basic LOG_* Functions" config LOG_DISABLE @@ -278,5 +288,5 @@ menu "SDK configuration" endmenu menu "Custom Components" - osource "${PINE64_SDK_PATH}/components/*/Kconfig" + osource "${OBLFR_SDK_PATH}/components/*/Kconfig" endmenu diff --git a/cmake/bflbsdk.cmake b/cmake/bflbsdk.cmake index 4a20dbe..f5c6dc6 100644 --- a/cmake/bflbsdk.cmake +++ b/cmake/bflbsdk.cmake @@ -1,4 +1,51 @@ cmake_minimum_required(VERSION 3.15) + +include(proj.conf OPTIONAL RESULT_VARIABLE proj_conf_file) + +if(CONFIG_BFLB_BOARD) + set(BOARD ${CONFIG_BFLB_BOARD}) +endif() +if(CONFIG_BFLB_CHIP) + set(CHIP ${CONFIG_BFLB_CHIP}) +endif() +if(CONFIG_BFLB_CPU_ID) + set(CPU_ID ${CONFIG_BFLB_CPU_ID}) +endif() + +if(BOARD STREQUAL "ox64") + set(CHIP "bl808") +elseif(BOARD STREQUAL "m1sdock") + set(CHIP "bl808") +elseif(BOARD STREQUAL "bl808dk") + set(CHIP "bl808") + unset(BOARD_DIR CACHE) +elseif(BOARD STREQUAL "m0sdock") + set(CHIP "bl616") +elseif(BOARD STREQUAL "bl616dk") + set(CHIP "bl616") + unset(BOARD_DIR CACHE) +elseif(BOARD STREQUAL "m0sense") + set(CHIP "bl702") +endif() + +if(CHIP STREQUAL "bl808") +if(NOT CPU_ID) + set(CPU_ID "m0") +endif() +endif() + +if(CPU_ID) + message(STATUS "BOARD: ${BOARD}, CHIP: ${CHIP}, CPU_ID: ${CPU_ID}") +else() + message(STATUS "BOARD: ${BOARD}, CHIP: ${CHIP}") +endif() +if(BOARD_DIR) + message(STATUS "BOARD_DIR: ${BOARD_DIR}") +endif() + + find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) include(${SDK_PATH}/cmake/kconfig.cmake) +add_subdirectory(${SDK_PATH}/bsp/common/ bsp_common) +#add_subdirectory(${SDK_PATH}/components/ components) diff --git a/cmake/kconfig.cmake b/cmake/kconfig.cmake index f3d9cd6..78aef99 100644 --- a/cmake/kconfig.cmake +++ b/cmake/kconfig.cmake @@ -1,13 +1,33 @@ -message("Running KConfig") add_custom_target(config-dir ALL COMMAND ${CMAKE_COMMAND} -E make_directory config) add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/config/sdkconfig.h COMMAND ${SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${SDK_PATH} --header ${CMAKE_CURRENT_BINARY_DIR}/config/ --projectdir ${CMAKE_CURRENT_SOURCE_DIR} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/sdkconfig - COMMENT "Generating SDKConfig" + COMMENT "Generating config/sdkconfig.h" VERBATIM) target_sources(app PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/config/sdkconfig.h) -target_include_directories(app PUBLIC ${CMAKE_CURRENT_BINARY_DIR}/config) +sdk_add_include_directories(${CMAKE_CURRENT_BINARY_DIR}/config) + +add_custom_target(config + COMMAND ${SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${SDK_PATH} --menuconfig 1 --cmake 1 --projectdir ${CMAKE_CURRENT_SOURCE_DIR} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID}) + +add_custom_command(OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/sdkconfig + COMMAND ${SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${SDK_PATH} --projectdir ${CMAKE_CURRENT_SOURCE_DIR} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} + COMMENT "Generating sdkconfig" + VERBATIM) + +add_custom_target(proj.conf + COMMAND ${SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${SDK_PATH} --cmake 1 --projectdir ${CMAKE_CURRENT_SOURCE_DIR} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/sdkconfig + COMMENT "Generating proj.conf" + VERBATIM) +set_property( + DIRECTORY + APPEND + PROPERTY CMAKE_CONFIGURE_DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/proj.conf +) + +message(STATUS "SDK: proj.conf file: ${proj_conf_file}") \ No newline at end of file diff --git a/cmake/project.build b/cmake/project.build index bb7f287..65a11c2 100644 --- a/cmake/project.build +++ b/cmake/project.build @@ -1,31 +1,32 @@ -BL_SDK_BASE ?= ${PINE64_SDK_PATH}/../bl_mcu_sdk +BL_SDK_BASE ?= ${OBLFR_SDK_PATH}/../bl_mcu_sdk export BL_SDK_BASE -CHIP ?= bl808 + BOARD ?= ox64 -CPU_ID ?= m0 -BOARD_DIR ?= ${PINE64_SDK_PATH}/bsp +BOARD_DIR ?= ${OBLFR_SDK_PATH}/bsp CROSS_COMPILE ?= riscv64-unknown-elf- -.PHONY:config - default: proj.conf @$(MAKE) build -sdkconfig: - @echo "Generating sdkconfig from sdkconfig.default" - @${PINE64_SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${PINE64_SDK_PATH} --projectdir ${PWD} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} -proj.conf: sdkconfig - @echo "Generating proj.conf from sdkconfig" - @${PINE64_SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${PINE64_SDK_PATH} --cmake 1 --projectdir ${PWD} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} +config: proj.conf + cd build && make config -config: - @${PINE64_SDK_PATH}/tools/kconfig/gensdkconfig.py --sdkpath ${PINE64_SDK_PATH} --menuconfig 1 --cmake 1 --projectdir ${PWD} --env BFLB_BOARD_DIR=${BOARD_DIR} --env BFLB_BOARD=${BOARD} --env BFLB_CHIP=${CHIP} --env BFLB_CPU_ID=${CPU_ID} +proj.conf: + $(CMAKE) -S . -B build -G $(cmake_generator) $(cmake_definition) + cd build && make proj.conf include $(BL_SDK_BASE)/project.build +distclean: clean + -@rm -rf sdkconfig || true + +clean: + -@rm -rf build || true + -@rm -f proj.conf || true +.PHONY:config clean distclean default \ No newline at end of file diff --git a/tools/kconfig/gensdkconfig.py b/tools/kconfig/gensdkconfig.py index 890e9c9..2bc6220 100755 --- a/tools/kconfig/gensdkconfig.py +++ b/tools/kconfig/gensdkconfig.py @@ -41,12 +41,12 @@ def _cmake_contents(kconfig, header): def write_config(kconfig): filename = args.projectdir + "/" + "sdkconfig" - print("-- Write Project config to: " + filename) + #print("-- Write Project config to: " + filename) kconfig.write_config(filename) def write_cmake(kconfig): filename = args.projectdir + "/" + "proj.conf" - print("-- Write CMake config to: " + filename) + #print("-- Write CMake config to: " + filename) cmake_conf_header = "# Generated by KConfig!\n" cmake_conf_header += "### DO NOT edit this file!! ###\n" cmake_conf_header += "### Run make config instead ###\n\n" @@ -63,8 +63,8 @@ def write_cmake(kconfig): def write_header(kconfig): filename = "sdkconfig.h" - print("-- write C header file at: " + args.header + "/" + filename) - print(kconfig.write_autoconf( args.header + "/" + filename)) + #print("-- write C header file at: " + args.header + "/" + filename) + kconfig.write_autoconf( args.header + "/" + filename) OUTPUT_FORMATS = { "makefile": write_config, @@ -123,7 +123,8 @@ for env in args.env: out_format = ["makefile", "header", "cmake"] os.environ["KCONFIG_CONFIG"] = args.projectdir + "/sdkconfig" os.environ["srctree"] = args.projectdir -print("Project Config File Path: " + os.environ["KCONFIG_CONFIG"]) +os.environ["OBLFR_SDK_PATH"] = args.sdkpath +#print("Project Config File Path: " + os.environ["KCONFIG_CONFIG"]) sdkconfig = args.sdkpath + "/cmake/SDKconfig" @@ -133,15 +134,15 @@ kconfig.warn = True if args.defaults: for path in args.defaults: path = args.projectdir + "/" + path - print("Attemping to load default config: " + path) + #print("Attemping to load default config: " + path) if os.path.exists(path): - print("Load Default config: " + path) + #print("Load Default config: " + path) kconfig.load_config(path, replace=False) - else: - print("Warning: Default Config file not found: " + path) + #else: + #print("Warning: Default Config file not found: " + path) if os.path.exists(args.projectdir + "/sdkconfig"): - print("Load Project config: " + args.projectdir + "/sdkconfig") + #print("Load Project config: " + args.projectdir + "/sdkconfig") kconfig.load_config(args.projectdir + "/sdkconfig")