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Merge branch 'openbouffalo:master' into networking

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Justin Hammond 2023-03-10 12:52:17 +08:00 • committed by GitHub
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44 changed files with 1814 additions and 97 deletions
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13
README.md
View file

@ -39,6 +39,19 @@ if your bl_mcu_sdk is located in a different path, then the following will work:
* lowload firmware is used to assist Linux to boot on the BL808 Device. Please consult the [OpenBouffalo Buildroot repo](https://github.com/openbouffalo/buildroot_bouffalo) for more information
## Flashing Different CPU's
You can use "make flash" to flash the firmware from the commandline instead of using the BLDevCube. By Default, the apps are configured to flash to the M0 core, but you can specify the core to flash to by modifying the flash_prog_cfg.ini file in the root of the project.
* For M0 set address = 0x000000
* For D0 set address = 0x100000
* For LP set address = 0x200000
If you are flashing from BLDevCube, set the CPU to Group0 and use the following addresses for the different cores:
* For M0 set address = 0x58000000
* For D0 set address = 0x58100000
* For LP set address = 0x58200000
(you may need to modify the cmake/flash.cmake file to specify the correct serial port for your device, or during the initial build, set the COMX enviroment variable to your serial port)
## Configuring SDK Features
The Bouffalo SDK provides numerous configuration options, enabled via the proj.conf in a standard bl_mcu_sdk project. This repository has enabled menuconfig, to give a graphical interface to enable/disable features in the SDK. You can enter the configuration dialog by running in each applications directory:

2
apps/d0_lowload/CMakeLists.txt
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@ -20,6 +20,8 @@ target_sources(app PRIVATE
target_compile_options(app PRIVATE -ggdb -Os)
sdk_add_link_options(-ufw_header)
sdk_set_main_file(src/main.c)
sdk_set_linker_script(bl808_flash_d0.ld)
project(d0_lowload)

7
apps/d0_lowload/bl808_flash_d0.ld
View file

@ -24,6 +24,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 1M
itcm_memory (rx) : ORIGIN = 0x3F000000, LENGTH = 12K
dtcm_memory (rx) : ORIGIN = 0x3F003000, LENGTH = 4K
@ -34,7 +35,11 @@ MEMORY
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);

11
apps/d0_lowload/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/d0_lowload_bl808_d0.bin
address = 0x100000

12
apps/d0_lowload/src/main.c
View file

@ -38,7 +38,7 @@ extern void unlz4(const void *aSource, void *aDestination, uint32_t FileLen);
#define VM_LINUX_DST_ADDR 0x50000000
#define OPENSBI_DST_ADDR 0x3EF80000
#define DTB_DST_ADDR 0x51ff8000
#define BOOT_HDR_SRC_ADDR 0x58080000
#define BOOT_HDR_SRC_ADDR 0x5d5ff000
static struct bflb_device_s *uart0;
@ -138,7 +138,17 @@ void linux_load()
{
LOG_I("low_load start... \r\n");
// for (int32_t i = 0; i < 10000000; i += 4) {
// vm_boot_header_t *header = (vm_boot_header_t *)BOOT_HDR_SRC_ADDR + i;
// if (header->magic == 0x4c4d5642) {
// LOG_I("Header at %d %p\r\n", i, header);
// break;
// }
// }
vm_boot_header_t *header = (vm_boot_header_t *)BOOT_HDR_SRC_ADDR;
LOG_I("Header at 0x%08x\r\n", BOOT_HDR_SRC_ADDR);
if (header->magic != 0x4c4d5642) {
LOG_E("invalid boot header magic: 0x%08x\r\n", header->magic);
return;

11
apps/examples/button/flash_prog_cfg.ini Normal file
View file

@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/button_$(CHIPNAME).bin
address = 0x000000

11
apps/examples/indicator/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/indicator_$(CHIPNAME).bin
address = 0x000000

11
apps/examples/nvkvs/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/nvkvsdemo_$(CHIPNAME).bin
address = 0x000000

11
apps/examples/rpmsg/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/rpmsgdemo_$(CHIPNAME).bin
address = 0x000000

11
apps/examples/timer/flash_prog_cfg.ini Normal file
View file

@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/timer_$(CHIPNAME).bin
address = 0x000000

11
apps/helloworld/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/helloworld_$(CHIPNAME).bin
address = 0x000000

11
apps/linux_mgr/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/linux_mgr_bl808_m0.bin
address = 0x000000

11
apps/m0_lowload/flash_prog_cfg.ini Normal file
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@ -0,0 +1,11 @@
[cfg]
# 0: no erase, 1:programmed section erase, 2: chip erase
erase = 1
# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
skip_mode = 0x0, 0x0
# 0: not use isp mode, #1: isp mode
boot2_isp_mode = 0
[FW]
filedir = ./build/build_out/m0_lowload_bl808_m0.bin
address = 0x000000

2
apps/m0_lowload/sdkconfig.default
View file

@ -1,3 +1,3 @@
CONFIG_COMPONENT_MAILBOX=y
CONFIG_COMPONENT_MAILBOX_IRQFWD_SDH=y
CONFIG_COMPONENT_MAILBOX_IRQFWD_GPIO=y
CONFIG_COMPONENT_MAILBOX_IRQFWD_GPIO=y

3
bsp/common/bl616/CMakeLists.txt
View file

@ -1,6 +1,7 @@
sdk_add_include_directories(include)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl616_bsp.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl616_bsp.c ${CMAKE_CURRENT_SOURCE_DIR}/src/fw_header.c)
sdk_add_link_options(-ufw_header)
sdk_set_linker_script(bl616_flash.ld)

24
bsp/common/bl616/bl616_flash.ld
View file

@ -185,28 +185,7 @@ SECTIONS
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
@ -294,6 +273,7 @@ SECTIONS
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
KEEP(*(.img_buf*))
. = ALIGN(4);
__psram_data_end__ = .;

200
bsp/common/bl616/include/fw_header.h Normal file
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@ -0,0 +1,200 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t rsvd0;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd1; /* rsvd */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 12 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg; /* 16 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd; /* 4 */
uint32_t crc32; /* 4 */
};
#define BFLB_FW_LENGTH_OFFSET 132
#define BFLB_FW_HASH_OFFSET 136
#endif

169
bsp/common/bl616/src/fw_header.c Normal file
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@ -0,0 +1,169 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x05, /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
.clk_cfg.cfg.mcu_clk_div = 0x00, /*!< mcu_clk divider */
.clk_cfg.cfg.mcu_bclk_div = 0x00, /*!< mcu_bclk divider */
.clk_cfg.cfg.mcu_pbclk_div = 0x03, /*!< mcu_pclk divider */
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01, /*!< emi clock divider */
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
#ifdef BFLB_BOOT2
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
#else
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
#endif
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg.halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg.cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg.cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.rsvd = 0x0,
/* image_address_offset */
.cpu_cfg.image_address_offset = 0x0,
.cpu_cfg.rsvd1 = 0xA0000000, /* rsvd */
.cpu_cfg.msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef
};

3
bsp/common/bl702/CMakeLists.txt
View file

@ -1,6 +1,7 @@
sdk_add_include_directories(include)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl702_bsp.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl702_bsp.c ${CMAKE_CURRENT_SOURCE_DIR}/src/fw_header.c)
sdk_add_link_options(-ufw_header)
sdk_set_linker_script(bl702_flash.ld)

19
bsp/common/bl702/bl702_flash.ld
View file

@ -157,21 +157,7 @@ SECTIONS
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
*(.nocache_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
__ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
@ -188,6 +174,8 @@ SECTIONS
*(.sdata2)
*(.sdata2.*)
*(.nocache_ram)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
@ -215,6 +203,7 @@ SECTIONS
__noinit_data_start__ = .;
*(.noinit_data*)
*(.nocache_noinit_ram)
. = ALIGN(4);
__noinit_data_end__ = .;

170
bsp/common/bl702/include/fw_header.h Normal file
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@ -0,0 +1,170 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /*'BFXP'*/
uint32_t rivison;
struct boot_flash_cfg_t flash_cfg;
struct boot_clk_cfg_t clk_cfg;
union __attribute__((packed, aligned(1))) {
struct __attribute__((packed, aligned(1))) {
uint32_t sign : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface */
uint32_t rsvd_7_6 : 2; /* [7: 6] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_select : 1; /* [9] cache enable */
uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] ignore hash */
uint32_t halt_ap : 1; /* [18] halt ap */
uint32_t boot2_enable : 1; /* [19] boot2 enable */
uint32_t boot2_rollback : 1; /* [20] boot2 rollback */
uint32_t rsvd_31_21 : 11; /* [31: 21] rsvd */
} bval;
uint32_t wval;
} boot_cfg;
union __attribute__((packed, aligned(1))) {
uint32_t segment_cnt;
uint32_t img_len;
} img_segment_info;
uint32_t rsvd0; /* rsvd */
union __attribute__((packed, aligned(1))) {
uint32_t ramaddr;
uint32_t flashoffset;
} img_start;
uint32_t hash[32 / 4]; /*hash of the image*/
uint32_t boot2_pt_table_0; /* address of partition table 0 */
uint32_t boot2_pt_table_1; /* address of partition table 1 */
uint32_t crc32;
};
#define BFLB_FW_LENGTH_OFFSET 120
#define BFLB_FW_HASH_OFFSET 132
#endif

126
bsp/common/bl702/src/fw_header.c Normal file
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@ -0,0 +1,126 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */
.clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */
.clk_cfg.cfg.hclk_div = 0x00,
.clk_cfg.cfg.bclk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* boot cfg */
.boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/
.boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */
.boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/
.boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/
.boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */
.boot_cfg.bval.cache_select = 0x1, /* [9] for cache */
.boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */
.boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */
.boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/
.boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */
.boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */
.boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */
.boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */
.boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */
.boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
#ifdef BFLB_BOOT2
.img_start.flashoffset = 0x00002000, /* flash controller offset */
#else
.img_start.flashoffset = 0x00001000, /* flash controller offset */
#endif
.hash = { 0xdeadbeef }, /* hash of the image */
.boot2_pt_table_0 = 0x1000, /* address of partition table 0 */
.boot2_pt_table_1 = 0x2000, /* address of partition table 1 */
.crc32 = 0xdeadbeef /* 4 */
};

8
bsp/common/bl808/CMakeLists.txt
View file

@ -1,13 +1,15 @@
sdk_add_include_directories(include src)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_common.c)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_common.c ${CMAKE_CURRENT_SOURCE_DIR}/src/fw_header.c)
if(CPU_ID STREQUAL "d0")
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_d0.c)
elseif(CPU_ID STREQUAL "m0")
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_m0.c)
elseif(CPU_ID STREQUAL "lp")
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/bl808_bsp_lp.c)
else()
message(FATAL_ERROR "Unknown CPU")
endif()
sdk_add_link_options(-ufw_header)
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)

2
bsp/common/bl808/bl808_flash_d0.ld
View file

@ -35,7 +35,7 @@ SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header0))
KEEP(*(.fw_header))
} > fw_header_memory
.text :

254
bsp/common/bl808/bl808_flash_lp.ld Normal file
View file

@ -0,0 +1,254 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58020000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58020000, LENGTH = 1M
itcm_memory (rx) : ORIGIN = 0x2202C000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x22030000, LENGTH = 16K
nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
ram_memory (!rx) : ORIGIN = 0x22034000, LENGTH = 16K
xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
}
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for usb usbh_class_info */
. = ALIGN(4);
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
. = ALIGN(4);
__usbh_class_info_end__ = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_noinit_ram_data_start__ = .;
*(.nocache_noinit_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_noinit_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
}

12
bsp/common/bl808/bl808_flash_m0.ld
View file

@ -22,8 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K
fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
@ -36,13 +35,8 @@ SECTIONS
{
.fw_header0 :
{
KEEP(*(.fw_header0))
} > fw_header_memory0
.fw_header1 :
{
KEEP(*(.fw_header1))
} > fw_header_memory1
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{

213
bsp/common/bl808/include/fw_header.h Normal file
View file

@ -0,0 +1,213 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[8]; /* rsvd */
uint32_t rsvd1[8]; /* rsvd */
uint32_t rsvd3[5]; /* 20 */
uint32_t crc32; /* 4 */
};
#define BFLB_FW_LENGTH_OFFSET 140
#define BFLB_FW_HASH_OFFSET 144
#endif

3
bsp/common/bl808/src/bl808_bsp_common.h
View file

@ -7,4 +7,7 @@ extern void log_start(void);
void bl808_cpu_init(void);
#define CONFIG_D0_FLASH_ADDR 0x100000
#define CONFIG_LP_FLASH_ADDR 0x200000
#endif

55
bsp/common/bl808/src/bl808_bsp_lp.c Normal file
View file

@ -0,0 +1,55 @@
#include <bl808_glb.h>
#include <bflb_uart.h>
#include <bl808_bsp_common.h>
#include "log.h"
#include <mem.h>
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
static struct bflb_device_s *console;
extern void bflb_uart_set_console(struct bflb_device_s *dev);
static void console_init()
{
struct bflb_device_s *gpio;
gpio = bflb_device_get_by_name("gpio");
bflb_gpio_init(gpio, GPIO_PIN_18, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_19, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
struct bflb_uart_config_s cfg;
cfg.baudrate = 2000000;
cfg.data_bits = UART_DATA_BITS_8;
cfg.stop_bits = UART_STOP_BITS_1;
cfg.parity = UART_PARITY_NONE;
cfg.flow_ctrl = 0;
cfg.tx_fifo_threshold = 7;
cfg.rx_fifo_threshold = 7;
console = bflb_device_get_by_name("uart1");
bflb_uart_init(console, &cfg);
bflb_uart_set_console(console);
}
void bl808_cpu_init(void)
{
CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
bflb_irq_initialize();
console_init();
log_start();
bl_show_log();
}

21
bsp/common/bl808/src/bl808_bsp_m0.c
View file

@ -171,6 +171,7 @@ void bl808_cpu_init(void)
flag = bflb_irq_save();
GLB_Halt_CPU(GLB_CORE_ID_D0);
GLB_Halt_CPU(GLB_CORE_ID_LP);
ret = bflb_flash_init();
@ -202,17 +203,25 @@ void bl808_cpu_init(void)
}
}
#endif
/* set CPU D0 boot XIP address and flash address */
// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
// /* D0 boot from 0x58000000 */
// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
// /* D0 image offset on flash is 0x100000+0x1000(header) */
// bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0);
// /* set CPU D0 boot XIP address and flash address */
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
// // /* D0 boot from 0x58000000 */
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
// // /* D0 image offset on flash is 0x100000+0x1000(header) */
bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 2);
// /* LP boot from 0x58020000 */
GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x58020000);
// /* LP image offset on flash is CONFIG_LP_FLASH_ADDR+0x1000(header) */
bflb_sf_ctrl_set_flash_image_offset(CONFIG_LP_FLASH_ADDR + 0x1000, 2, SF_CTRL_FLASH_BANK1);
bflb_irq_restore(flag);
/* we do not check header at 0x100000, just boot */
GLB_Release_CPU(GLB_CORE_ID_D0);
GLB_Release_CPU(GLB_CORE_ID_LP);
/* release d0 and then do can run */
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);

208
bsp/common/bl808/src/fw_header.c Normal file
View file

@ -0,0 +1,208 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
#ifdef BFLB_BOOT2
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
#else
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
#endif
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.rsvd1[0] = 0x20000320,
.rsvd1[1] = 0x00000000,
.rsvd1[2] = 0x2000F038,
.rsvd1[3] = 0x18000000,
.crc32 = 0xdeadbeef /* 4 */
};

0
bsp/m0sdock/config/.gitkeep Normal file
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0
bsp/m0sense/config/.gitkeep Normal file
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0
bsp/m1sdock/config/.gitkeep Normal file
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0
bsp/ox64/config/.gitkeep Normal file
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30
cmake.patch
View file

@ -1,30 +0,0 @@
diff --git a/cmake/bflbsdk.cmake b/cmake/bflbsdk.cmake
index 8b7ceb2..65265aa 100644
--- a/cmake/bflbsdk.cmake
+++ b/cmake/bflbsdk.cmake
@@ -1,5 +1,7 @@
cmake_minimum_required(VERSION 3.15)
+include(proj.conf OPTIONAL RESULT_VARIABLE proj_conf_file)
+
if(CONFIG_BFLB_BOARD)
set(BOARD ${CONFIG_BFLB_BOARD})
endif()
@@ -10,6 +12,7 @@ if(CONFIG_BFLB_CPU_ID)
set(CPU_ID ${CONFIG_BFLB_CPU_ID})
endif()
+
if(BOARD STREQUAL "ox64")
set(CHIP "bl808")
elseif(BOARD STREQUAL "m1sdock")
@@ -41,9 +44,6 @@ if(BOARD_DIR)
message(STATUS "BOARD_DIR: ${BOARD_DIR}")
endif()
-include(proj.conf OPTIONAL RESULT_VARIABLE proj_conf_file)
-
-
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
include(${SDK_PATH}/cmake/kconfig.cmake)

2
cmake/bflbsdk.cmake
View file

@ -43,9 +43,11 @@ if(BOARD_DIR)
message(STATUS "BOARD_DIR: ${BOARD_DIR}")
endif()
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
include(${SDK_PATH}/cmake/sdk.cmake)
include(${SDK_PATH}/cmake/kconfig.cmake)
include(${SDK_PATH}/cmake/flash.cmake)
add_subdirectory(${SDK_PATH}/bsp/common/ bsp_common)
add_subdirectory(${SDK_PATH}/components/ components)

21
cmake/flash.cmake Normal file
View file

@ -0,0 +1,21 @@
if ($ENV{BAUDRATE})
set(BAUDRATE $ENV{BAUDRATE})
else()
set(BAUDRATE 2000000)
endif()
if ($ENV{COMX})
set(COMX $ENV{COMX})
else()
set(COMX /dev/ttyUSB1)
endif()
add_custom_target(flash
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
COMMAND $ENV{BL_SDK_BASE}/tools/bflb_tools/bouffalo_flash_cube/BLFlashCommand --interface=uart --baudrate=${BAUDRATE} --port=${COMX} --chipname=${CHIP} --cpu_id=${CPU_ID} --config=${CMAKE_CURRENT_SOURCE_DIR}/flash_prog_cfg.ini
)
add_custom_target(monitor
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
COMMAND tio --baudrate=${BAUDRATE} ${COMX}
)

7
cmake/project.build
View file

@ -24,8 +24,13 @@ distclean: clean
-@rm -rf build || true
-@rm -f sdkconfig || true
clean:
clean::
-@rm -f proj.conf || true
flash: default
@$(MAKE) -C build flash
monitor:
@$(MAKE) -C build monitor
.PHONY:config clean default distclean

2
components/mailbox/CMakeLists.txt
View file

@ -1,4 +1,4 @@
sdk_generate_library(oblfr_mailbox)
sdk_add_include_directories(include)
sdk_library_add_sources(${CMAKE_CURRENT_SOURCE_DIR}/src/oblfr_mailbox.c)
sdk_library_add_sources(${CMAKE_CURRENT_SOURCE_DIR}/src/oblfr_mailbox.c ${CMAKE_CURRENT_SOURCE_DIR}/src/oblfr_usb_peripheral.c )

10
components/mailbox/Kconfig
View file

@ -1,6 +1,6 @@
config COMPONENT_MAILBOX
bool "Mailbox Support for Linux"
default y
default y if BFLB_CHIP = "bl808"
help
Mailbox Component forwards IRQ's to the D0 core for Linux
support. Enable this component if you are running linux on
@ -27,6 +27,14 @@ config COMPONENT_MAILBOX_IRQFWD_USB
help
Curently disabled as USB is not working
config COMPONENT_MAILBOX_USB_HOST
depends on COMPONENT_MAILBOX_IRQFWD_USB
bool "Set USB to HOST mode"
default n
help
By default USB operates in peripheral mode. Set this to use the
USB adapter as a host device.
config COMPONENT_MAILBOX_IRQFWD_GPIO
bool "Enable IRQ forwarding for GPIO"
default y

86
components/mailbox/include/oblfr_usb_peripheral.h Normal file
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@ -0,0 +1,86 @@
// Portions Copyright () 2023 OpenBuffalo
/**
******************************************************************************
* @file usb_v2_reg.h
* @version V1.0
* @date 2022-08-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __OBLFR_USBPHY_H__
#include <stdint.h>
#include "oblfr_common.h"
oblfr_err_t setup_usb_peripheral(void);
// SUBSYSTEMS
#define BLFB_USB_BASE ((uint32_t)0x20072000)
#define BFLB_PDS_BASE ((uint32_t)0x2000e000)
// PDS REGISTERS
#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */
#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
// PDS REGISTER VALUES
/* 0x500 : usb_ctl */
#define PDS_REG_USB_SW_RST_N (1 << 0U)
#define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
#define PDS_REG_USB_WAKEUP (1 << 2U)
#define PDS_REG_USB_L1_WAKEUP (1 << 3U)
#define PDS_REG_USB_DRVBUS_POL (1 << 4U)
#define PDS_REG_USB_IDDIG (1 << 5U)
/* 0x504 : usb_phy_ctrl */
#define PDS_REG_USB_PHY_PONRST (1 << 0U)
#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U)
#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U)
#define PDS_REG_USB_PHY_PLLALIV (1 << 5U)
#define PDS_REG_PU_USB20_PSW (1 << 6U)
// USB REGS
#define USB_GLB_INT_OFFSET (0xC4) /* GLB_INT */
/* 0xC4 : GLB_INT */
#define USB_MDEV_INT (1 << 0U)
#define USB_MOTG_INT (1 << 1U)
#define USB_MHC_INT (1 << 2U)
#define USB_POLARITY (1 << 3U)
#endif

13
components/mailbox/src/oblfr_mailbox.c
View file

@ -14,6 +14,7 @@
#endif
#include "oblfr_mailbox.h"
#include "oblfr_usb_peripheral.h"
#define DBG_TAG "MBOX"
#include "log.h"
@ -254,7 +255,7 @@ oblfr_err_t setup_sdh_peripheral() {
}
#endif
#ifdef COMPONENT_MAILBOX_IRQFWD_EMAC
#ifdef CONFIG_COMPONENT_MAILBOX_IRQFWD_EMAC
static oblfr_err_t setup_emac_peripheral(void)
{
GLB_GPIO_Cfg_Type gpio_cfg;
@ -408,13 +409,20 @@ oblfr_err_t oblfr_mailbox_init()
}
#endif
#ifdef COMPONENT_MAILBOX_IRQFWD_EMAC
#ifdef CONFIG_COMPONENT_MAILBOX_IRQFWD_EMAC
if (setup_emac_peripheral() != SUCCESS) {
LOG_E("Failed to setup EMAC peripheral\r\n");
return OBLFR_ERR_ERROR;
}
#endif
#ifdef CONFIG_COMPONENT_MAILBOX_IRQFWD_USB
if (setup_usb_peripheral() != SUCCESS) {
LOG_E("Failed to setup USB peripheral\r\n");
return OBLFR_ERR_ERROR;
}
#endif
return OBLFR_OK;
}
@ -443,4 +451,3 @@ oblfr_err_t oblfr_mailbox_dump()
oblfr_mailbox_signal_unlock(false);
return OBLFR_OK;
}

115
components/mailbox/src/oblfr_usb_peripheral.c Normal file
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@ -0,0 +1,115 @@
//
// This is the bare bones code to power up the USB subsystem so that
// it can be used once the system is booted.
//
// All code was taken from the bl_mcu_sdk with adaptations, primarily
// from the file:
//
// drivers/lhal/src/bflb_usb_v2.c
//
// Portions Copyright (c) 2023 OpenBuffalo
/**
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include <arch/risc-v/riscv_arch.h>
#include <hardware/usb_v2_reg.h>
#include <board.h>
#include <bflb_mtimer.h>
#include "oblfr_usb_peripheral.h"
#define DBG_TAG "USB"
#include "log.h"
// Enable USB A mode instead of B
#define USB_HOST
oblfr_err_t setup_usb_peripheral(void)
{
uint32_t regval;
/* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
/* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
/* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
/* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
/* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
/* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
/* #1.2ms; wait UCLK */
/* wait(soc616_b0.usb_uclk); */
LOG_I("Initializing USB...\r\n");
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval |= PDS_REG_PU_USB20_PSW;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval |= PDS_REG_USB_PHY_PONRST;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
/* greater than 5T */
bflb_mtimer_delay_us(1);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval &= ~PDS_REG_USB_SW_RST_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
/* greater than 5T */
bflb_mtimer_delay_us(1);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval |= PDS_REG_USB_EXT_SUSP_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
/* wait UCLK 1.2ms */
bflb_mtimer_delay_ms(3);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval |= PDS_REG_USB_SW_RST_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
bflb_mtimer_delay_ms(2);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
#ifdef CONFIG_COMPONENT_MAILBOX_USB_HOST
LOG_I("USB Initialized in HOST mode\r\n");
regval &= ~PDS_REG_USB_IDDIG;
#else
LOG_I("USB Initialized in DEVICE mode\r\n");
regval |= PDS_REG_USB_IDDIG;
#endif
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
bflb_mtimer_delay_ms(10);
return OBLFR_OK;
}