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ARC: Use enough bits for determining page's cache color

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The current code uses 2 bits for determining page's dcache color, thus
sorting pages into 4 bins, whereas the aliasing dcache really has 2 bins
(8k page, 64k dcache - 4 way-set-assoc).
This can cause extraneous flushes - e.g. color 0 and 2.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2013-05-19 14:06:44 +05:30
parent 3e87974dec
commit 006dfb3c9c
1 changed files with 1 additions and 1 deletions
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2
arch/arc/include/asm/cacheflush.h
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@ -93,7 +93,7 @@ static inline int cache_is_vipt_aliasing(void)
#endif #endif
} }
#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3) #define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
/* /*
* checks if two addresses (after page aligning) index into same cache set * checks if two addresses (after page aligning) index into same cache set