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ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs

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When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown 2009-08-17 18:51:44 +01:00
parent 1ca04065c3
commit 0182dcc52c
1 changed files with 1 additions and 3 deletions
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4
sound/soc/codecs/wm8993.c
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@ -519,7 +519,7 @@ static int configure_clock(struct snd_soc_codec *codec)
dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
reg = wm8993_read(codec, WM8993_CLOCKING_2); reg = wm8993_read(codec, WM8993_CLOCKING_2);
reg &= ~WM8993_SYSCLK_SRC; reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
if (wm8993->mclk_rate > 13500000) { if (wm8993->mclk_rate > 13500000) {
reg |= WM8993_MCLK_DIV; reg |= WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate / 2; wm8993->sysclk_rate = wm8993->mclk_rate / 2;
@ -527,8 +527,6 @@ static int configure_clock(struct snd_soc_codec *codec)
reg &= ~WM8993_MCLK_DIV; reg &= ~WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate; wm8993->sysclk_rate = wm8993->mclk_rate;
} }
reg &= ~WM8993_MCLK_DIV;
reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
wm8993_write(codec, WM8993_CLOCKING_2, reg); wm8993_write(codec, WM8993_CLOCKING_2, reg);
break; break;