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microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver

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Modify the Microblaze PCI subsystem to work with the generic
drivers/pci/host/pcie-xilinx.c driver on Microblaze and Zynq.

[bhelgaas: changelog]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Bharat Kumar Gogada 2016-02-11 21:58:11 +05:30 • committed by Bjorn Helgaas
parent e5d4b2006c
commit 01cf9d524f
3 changed files with 14 additions and 47 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/microblaze/Kconfig
View file

@ -267,6 +267,9 @@ config PCI
config PCI_DOMAINS config PCI_DOMAINS
def_bool PCI def_bool PCI
config PCI_DOMAINS_GENERIC
def_bool PCI_DOMAINS
config PCI_SYSCALL config PCI_SYSCALL
def_bool PCI def_bool PCI

56
arch/microblaze/pci/pci-common.c
View file

@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
} }
EXPORT_SYMBOL_GPL(pci_address_to_pio); EXPORT_SYMBOL_GPL(pci_address_to_pio);
/*
* Return the domain number for this bus.
*/
int pci_domain_nr(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
return hose->global_number;
}
EXPORT_SYMBOL(pci_domain_nr);
/* This routine is meant to be used early during boot, when the /* This routine is meant to be used early during boot, when the
* PCI bus numbers have not yet been assigned, and you need to * PCI bus numbers have not yet been assigned, and you need to
* issue PCI config cycles to an OF device. * issue PCI config cycles to an OF device.
@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
void pcibios_fixup_bus(struct pci_bus *bus) void pcibios_fixup_bus(struct pci_bus *bus)
{ {
/* When called from the generic PCI probe, read PCI<->PCI bridge /* nothing to do */
* bases. This is -not- called when generating the PCI tree from
* the OF device-tree.
*/
if (bus->self != NULL)
pci_read_bridge_bases(bus);
/* Now fixup the bus bus */
pcibios_setup_bus_self(bus);
/* Now fixup devices on that bus */
pcibios_setup_bus_devices(bus);
} }
EXPORT_SYMBOL(pcibios_fixup_bus); EXPORT_SYMBOL(pcibios_fixup_bus);
static int skip_isa_ioresource_align(struct pci_dev *dev)
{
return 0;
}
/* /*
* We need to avoid collisions with `mirrored' VGA ports * We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the * and other strange ISA hardware, so we always want the
@ -899,20 +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
resource_size_t pcibios_align_resource(void *data, const struct resource *res, resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align) resource_size_t size, resource_size_t align)
{ {
struct pci_dev *dev = data; return res->start;
resource_size_t start = res->start;
if (res->flags & IORESOURCE_IO) {
if (skip_isa_ioresource_align(dev))
return start;
if (start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
}
return start;
} }
EXPORT_SYMBOL(pcibios_align_resource); EXPORT_SYMBOL(pcibios_align_resource);
int pcibios_add_device(struct pci_dev *dev)
{
dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
return 0;
}
EXPORT_SYMBOL(pcibios_add_device);
/* /*
* Reparent resource children of pr that conflict with res * Reparent resource children of pr that conflict with res
* under res, and make res replace those children. * under res, and make res replace those children.
@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
(unsigned long)hose->io_base_virt - _IO_BASE); (unsigned long)hose->io_base_virt - _IO_BASE);
} }
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
{
struct pci_controller *hose = bus->sysdata;
return of_node_get(hose->dn);
}
static void pcibios_scan_phb(struct pci_controller *hose) static void pcibios_scan_phb(struct pci_controller *hose)
{ {
LIST_HEAD(resources); LIST_HEAD(resources);

2
drivers/pci/host/Kconfig
View file

@ -81,7 +81,7 @@ config PCI_KEYSTONE
config PCIE_XILINX config PCIE_XILINX
bool "Xilinx AXI PCIe host bridge support" bool "Xilinx AXI PCIe host bridge support"
depends on ARCH_ZYNQ depends on ARCH_ZYNQ || MICROBLAZE
help help
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
Host Bridge driver. Host Bridge driver.