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MIPS: DSP: Set all register masks to 0x3ff.

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0x2ff was a typo and the value 0x1f of DSP_MASK was refering to an old
version of the documentation.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2005-12-06 09:43:20 +00:00 • committed by
parent f12555d24c
commit 07a801def4
1 changed files with 3 additions and 3 deletions
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6
include/asm-mips/dsp.h
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@ -16,7 +16,7 @@
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#define DSP_DEFAULT 0x00000000 #define DSP_DEFAULT 0x00000000
#define DSP_MASK 0x1f #define DSP_MASK 0x3ff
#define __enable_dsp_hazard() \ #define __enable_dsp_hazard() \
do { \ do { \
@ -48,7 +48,7 @@ do { \
tsk->thread.dsp.dspr[3] = mflo2(); \ tsk->thread.dsp.dspr[3] = mflo2(); \
tsk->thread.dsp.dspr[4] = mfhi3(); \ tsk->thread.dsp.dspr[4] = mfhi3(); \
tsk->thread.dsp.dspr[5] = mflo3(); \ tsk->thread.dsp.dspr[5] = mflo3(); \
tsk->thread.dsp.dspcontrol = rddsp(0x2ff); \ tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \
} while (0) } while (0)
#define save_dsp(tsk) \ #define save_dsp(tsk) \
@ -65,7 +65,7 @@ do { \
mtlo2(tsk->thread.dsp.dspr[3]); \ mtlo2(tsk->thread.dsp.dspr[3]); \
mthi3(tsk->thread.dsp.dspr[4]); \ mthi3(tsk->thread.dsp.dspr[4]); \
mtlo3(tsk->thread.dsp.dspr[5]); \ mtlo3(tsk->thread.dsp.dspr[5]); \
wrdsp(tsk->thread.dsp.dspcontrol, 0x2ff); \ wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \
} while (0) } while (0)
#define restore_dsp(tsk) \ #define restore_dsp(tsk) \