From 2dcb90ef4f89a871f6ee816ff30f7eb0037ada74 Mon Sep 17 00:00:00 2001 From: Oleg Moroz Date: Sat, 4 Jan 2014 13:53:14 +0400 Subject: [PATCH 1/3] can: sja1000: add support for Elcus CAN200PCI This patch adds support for Elcus CAN200PCI card. Signed-off-by: Oleg Moroz Signed-off-by: Marc Kleine-Budde --- drivers/net/can/sja1000/plx_pci.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/sja1000/plx_pci.c b/drivers/net/can/sja1000/plx_pci.c index 5df7f9848823..fbb61a0d901f 100644 --- a/drivers/net/can/sja1000/plx_pci.c +++ b/drivers/net/can/sja1000/plx_pci.c @@ -44,7 +44,8 @@ MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, " "esd CAN-PCI/PMC/266, " "esd CAN-PCIe/2000, " "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), " - "IXXAT PC-I 04/PCI") + "IXXAT PC-I 04/PCI, " + "ELCUS CAN-200-PCI") MODULE_LICENSE("GPL v2"); #define PLX_PCI_MAX_CHAN 2 @@ -122,6 +123,11 @@ struct plx_pci_card { #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 +#define CAN200PCI_DEVICE_ID 0x9030 +#define CAN200PCI_VENDOR_ID 0x10b5 +#define CAN200PCI_SUB_DEVICE_ID 0x0301 +#define CAN200PCI_SUB_VENDOR_ID 0xe1c5 + #define IXXAT_PCI_VENDOR_ID 0x10b5 #define IXXAT_PCI_DEVICE_ID 0x9050 #define IXXAT_PCI_SUB_SYS_ID 0x2540 @@ -233,6 +239,14 @@ static struct plx_pci_card_info plx_pci_card_info_cti = { /* based on PLX9030 */ }; +static struct plx_pci_card_info plx_pci_card_info_elcus = { + "Eclus CAN-200-PCI", 2, + PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, + {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, + &plx_pci_reset_common + /* based on PLX9030 */ +}; + static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = { { /* Adlink PCI-7841/cPCI-7841 */ @@ -318,6 +332,13 @@ static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = { 0, 0, (kernel_ulong_t)&plx_pci_card_info_cti }, + { + /* Elcus CAN-200-PCI */ + CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, + CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID, + 0, 0, + (kernel_ulong_t)&plx_pci_card_info_elcus + }, { 0,} }; MODULE_DEVICE_TABLE(pci, plx_pci_tbl); From 40d451181a7fa57e32bca4632ae7b22f80861a73 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Mon, 6 Jan 2014 05:21:03 -0800 Subject: [PATCH 2/3] can: Disable flexcan driver build for big endian CPU on ARM Building arm:allmodconfig fails with flexcan.c: In function 'flexcan_read': flexcan.c:243:2: error: implicit declaration of function 'in_be32' flexcan.c: In function 'flexcan_write': flexcan.c:248:2: error: implicit declaration of function 'out_be32' in_be32 and out_be32 do not (or no longer) exist for ARM targets. Disable the build for ARM on big endian CPUs. Signed-off-by: Guenter Roeck Signed-off-by: Marc Kleine-Budde --- drivers/net/can/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig index 9e7d95dae2c7..d447b881bbde 100644 --- a/drivers/net/can/Kconfig +++ b/drivers/net/can/Kconfig @@ -104,7 +104,7 @@ config CAN_JANZ_ICAN3 config CAN_FLEXCAN tristate "Support for Freescale FLEXCAN based chips" - depends on ARM || PPC + depends on (ARM && CPU_LITTLE_ENDIAN) || PPC ---help--- Say Y here if you want to support for Freescale FlexCAN. From ea79c1c18520c3a60a2fc8193e2fb58710812d4e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Sat, 11 Jan 2014 19:11:24 +0100 Subject: [PATCH 3/3] can: ti_hecc: fix endianness related sparse warning This patch fixes the following sparse warning, which occurs in casts when accessing the data in the CAN frames (struct can_frame) in the RX and TX routines: drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:521:17: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:524:25: warning: cast to restricted __be32 drivers/net/can/ti_hecc.c:572:28: warning: incorrect type in assignment (different base types) drivers/net/can/ti_hecc.c:572:28: expected unsigned int [unsigned] [usertype] drivers/net/can/ti_hecc.c:572:28: got restricted __be32 [usertype] drivers/net/can/ti_hecc.c:575:40: warning: incorrect type in assignment (different base types) drivers/net/can/ti_hecc.c:575:40: expected unsigned int [unsigned] [usertype] drivers/net/can/ti_hecc.c:575:40: got restricted __be32 [usertype] As the data is indeed big endian, use "__be32" instead of "u32", when casting it. Signed-off-by: Marc Kleine-Budde --- drivers/net/can/ti_hecc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c index 60d95b44d0f7..3e2bd9d635ab 100644 --- a/drivers/net/can/ti_hecc.c +++ b/drivers/net/can/ti_hecc.c @@ -518,10 +518,10 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) data = (cf->can_id & CAN_SFF_MASK) << 18; hecc_write_mbx(priv, mbxno, HECC_CANMID, data); hecc_write_mbx(priv, mbxno, HECC_CANMDL, - be32_to_cpu(*(u32 *)(cf->data))); + be32_to_cpu(*(__be32 *)(cf->data))); if (cf->can_dlc > 4) hecc_write_mbx(priv, mbxno, HECC_CANMDH, - be32_to_cpu(*(u32 *)(cf->data + 4))); + be32_to_cpu(*(__be32 *)(cf->data + 4))); else *(u32 *)(cf->data + 4) = 0; can_put_echo_skb(skb, ndev, mbxno); @@ -569,12 +569,10 @@ static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno) cf->can_id |= CAN_RTR_FLAG; cf->can_dlc = get_can_dlc(data & 0xF); data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); - *(u32 *)(cf->data) = cpu_to_be32(data); + *(__be32 *)(cf->data) = cpu_to_be32(data); if (cf->can_dlc > 4) { data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); - *(u32 *)(cf->data + 4) = cpu_to_be32(data); - } else { - *(u32 *)(cf->data + 4) = 0; + *(__be32 *)(cf->data + 4) = cpu_to_be32(data); } spin_lock_irqsave(&priv->mbx_lock, flags); hecc_clear_bit(priv, HECC_CANME, mbx_mask);