mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-06-26 16:41:25 +00:00
powerpc updates for 4.2
- Disable the 32-bit vdso when building LE, so we can build with a 64-bit only
toolchain.
- EEH fixes from Gavin & Richard.
- Enable the sys_kcmp syscall from Laurent.
- Sysfs control for fastsleep workaround from Shreyas.
- Expose OPAL events as an irq chip by Alistair.
- MSI ops moved to pci_controller_ops by Daniel.
- Fix for kernel to userspace backtraces for perf from Anton.
- Merge pseries and pseries_le defconfigs from Cyril.
- CXL in-kernel API from Mikey.
- OPAL prd driver from Jeremy.
- Fix for DSCR handling & tests from Anshuman.
- Powernv flash mtd driver from Cyril.
- Dynamic DMA Window support on powernv from Alexey.
- LLVM clang fixes & workarounds from Anton.
- Reworked version of the patch to abort syscalls when transactional.
- Fix the swap encoding to support 4TB, from Aneesh.
- Various fixes as usual.
- Freescale updates from Scott: Highlights include more 8xx optimizations, an
e6500 hugetlb optimization, QMan device tree nodes, t1024/t1023 support, and
various fixes and cleanup.
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Merge tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
Pull powerpc updates from Michael Ellerman:
- disable the 32-bit vdso when building LE, so we can build with a
64-bit only toolchain.
- EEH fixes from Gavin & Richard.
- enable the sys_kcmp syscall from Laurent.
- sysfs control for fastsleep workaround from Shreyas.
- expose OPAL events as an irq chip by Alistair.
- MSI ops moved to pci_controller_ops by Daniel.
- fix for kernel to userspace backtraces for perf from Anton.
- merge pseries and pseries_le defconfigs from Cyril.
- CXL in-kernel API from Mikey.
- OPAL prd driver from Jeremy.
- fix for DSCR handling & tests from Anshuman.
- Powernv flash mtd driver from Cyril.
- dynamic DMA Window support on powernv from Alexey.
- LLVM clang fixes & workarounds from Anton.
- reworked version of the patch to abort syscalls when transactional.
- fix the swap encoding to support 4TB, from Aneesh.
- various fixes as usual.
- Freescale updates from Scott: Highlights include more 8xx
optimizations, an e6500 hugetlb optimization, QMan device tree nodes,
t1024/t1023 support, and various fixes and cleanup.
* tag 'powerpc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (180 commits)
cxl: Fix typo in debug print
cxl: Add CXL_KERNEL_API config option
powerpc/powernv: Fix wrong IOMMU table in pnv_ioda_setup_bus_dma()
powerpc/mm: Change the swap encoding in pte.
powerpc/mm: PTE_RPN_MAX is not used, remove the same
powerpc/tm: Abort syscalls in active transactions
powerpc/iommu/ioda2: Enable compile with IOV=on and IOMMU_API=off
powerpc/include: Add opal-prd to installed uapi headers
powerpc/powernv: fix construction of opal PRD messages
powerpc/powernv: Increase opal-irqchip initcall priority
powerpc: Make doorbell check preemption safe
powerpc/powernv: pnv_init_idle_states() should only run on powernv
macintosh/nvram: Remove as unused
powerpc: Don't use gcc specific options on clang
powerpc: Don't use -mno-strict-align on clang
powerpc: Only use -mtraceback=no, -mno-string and -msoft-float if toolchain supports it
powerpc: Only use -mabi=altivec if toolchain supports it
powerpc: Fix duplicate const clang warning in user access code
vfio: powerpc/spapr: Support Dynamic DMA windows
vfio: powerpc/spapr: Register memory and define IOMMU v2
...
This commit is contained in:
Linus Torvalds
commit
08d183e3c1
210 changed files with 9267 additions and 2225 deletions
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@ -36,6 +36,8 @@
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/* Two-stage IOMMU */
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#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
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#define VFIO_SPAPR_TCE_v2_IOMMU 7
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/*
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* The IOCTL interface is designed for extensibility by embedding the
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* structure length (argsz) and flags into structures passed between
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@ -442,6 +444,23 @@ struct vfio_iommu_type1_dma_unmap {
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/* -------- Additional API for SPAPR TCE (Server POWERPC) IOMMU -------- */
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/*
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* The SPAPR TCE DDW info struct provides the information about
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* the details of Dynamic DMA window capability.
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*
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* @pgsizes contains a page size bitmask, 4K/64K/16M are supported.
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* @max_dynamic_windows_supported tells the maximum number of windows
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* which the platform can create.
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* @levels tells the maximum number of levels in multi-level IOMMU tables;
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* this allows splitting a table into smaller chunks which reduces
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* the amount of physically contiguous memory required for the table.
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*/
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struct vfio_iommu_spapr_tce_ddw_info {
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__u64 pgsizes; /* Bitmap of supported page sizes */
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__u32 max_dynamic_windows_supported;
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__u32 levels;
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};
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/*
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* The SPAPR TCE info struct provides the information about the PCI bus
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* address ranges available for DMA, these values are programmed into
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@ -452,14 +471,17 @@ struct vfio_iommu_type1_dma_unmap {
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* addresses too so the window works as a filter rather than an offset
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* for IOVA addresses.
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*
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* A flag will need to be added if other page sizes are supported,
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* so as defined here, it is always 4k.
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* Flags supported:
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* - VFIO_IOMMU_SPAPR_INFO_DDW: informs the userspace that dynamic DMA windows
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* (DDW) support is present. @ddw is only supported when DDW is present.
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*/
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struct vfio_iommu_spapr_tce_info {
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__u32 argsz;
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__u32 flags; /* reserved for future use */
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__u32 flags;
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#define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) /* DDW supported */
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__u32 dma32_window_start; /* 32 bit window start (bytes) */
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__u32 dma32_window_size; /* 32 bit window size (bytes) */
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struct vfio_iommu_spapr_tce_ddw_info ddw;
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};
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#define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12)
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@ -470,12 +492,23 @@ struct vfio_iommu_spapr_tce_info {
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* - unfreeze IO/DMA for frozen PE;
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* - read PE state;
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* - reset PE;
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* - configure PE.
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* - configure PE;
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* - inject EEH error.
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*/
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struct vfio_eeh_pe_err {
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__u32 type;
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__u32 func;
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__u64 addr;
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__u64 mask;
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};
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struct vfio_eeh_pe_op {
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__u32 argsz;
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__u32 flags;
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__u32 op;
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union {
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struct vfio_eeh_pe_err err;
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};
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};
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#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */
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@ -492,9 +525,70 @@ struct vfio_eeh_pe_op {
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#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */
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#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */
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#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */
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#define VFIO_EEH_PE_INJECT_ERR 9 /* Inject EEH error */
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#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21)
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/**
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* VFIO_IOMMU_SPAPR_REGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 17, struct vfio_iommu_spapr_register_memory)
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*
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* Registers user space memory where DMA is allowed. It pins
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* user pages and does the locked memory accounting so
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* subsequent VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA calls
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* get faster.
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*/
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struct vfio_iommu_spapr_register_memory {
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__u32 argsz;
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__u32 flags;
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__u64 vaddr; /* Process virtual address */
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__u64 size; /* Size of mapping (bytes) */
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};
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#define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17)
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/**
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* VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY - _IOW(VFIO_TYPE, VFIO_BASE + 18, struct vfio_iommu_spapr_register_memory)
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*
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* Unregisters user space memory registered with
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* VFIO_IOMMU_SPAPR_REGISTER_MEMORY.
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* Uses vfio_iommu_spapr_register_memory for parameters.
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*/
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#define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18)
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/**
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* VFIO_IOMMU_SPAPR_TCE_CREATE - _IOWR(VFIO_TYPE, VFIO_BASE + 19, struct vfio_iommu_spapr_tce_create)
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*
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* Creates an additional TCE table and programs it (sets a new DMA window)
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* to every IOMMU group in the container. It receives page shift, window
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* size and number of levels in the TCE table being created.
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*
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* It allocates and returns an offset on a PCI bus of the new DMA window.
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*/
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struct vfio_iommu_spapr_tce_create {
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__u32 argsz;
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__u32 flags;
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/* in */
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__u32 page_shift;
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__u64 window_size;
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__u32 levels;
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/* out */
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__u64 start_addr;
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};
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#define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19)
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/**
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* VFIO_IOMMU_SPAPR_TCE_REMOVE - _IOW(VFIO_TYPE, VFIO_BASE + 20, struct vfio_iommu_spapr_tce_remove)
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*
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* Unprograms a TCE table from all groups in the container and destroys it.
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* It receives a PCI bus offset as a window id.
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*/
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struct vfio_iommu_spapr_tce_remove {
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__u32 argsz;
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__u32 flags;
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/* in */
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__u64 start_addr;
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};
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#define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20)
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/* ***************************************************************** */
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#endif /* _UAPIVFIO_H */
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@ -32,10 +32,32 @@ struct cxl_ioctl_start_work {
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#define CXL_START_WORK_ALL (CXL_START_WORK_AMR |\
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CXL_START_WORK_NUM_IRQS)
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/* Possible modes that an afu can be in */
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#define CXL_MODE_DEDICATED 0x1
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#define CXL_MODE_DIRECTED 0x2
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/* possible flags for the cxl_afu_id flags field */
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#define CXL_AFUID_FLAG_SLAVE 0x1 /* In directed-mode afu is in slave mode */
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struct cxl_afu_id {
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__u64 flags; /* One of CXL_AFUID_FLAG_X */
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__u32 card_id;
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__u32 afu_offset;
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__u32 afu_mode; /* one of the CXL_MODE_X */
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__u32 reserved1;
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__u64 reserved2;
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__u64 reserved3;
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__u64 reserved4;
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__u64 reserved5;
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__u64 reserved6;
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};
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/* ioctl numbers */
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#define CXL_MAGIC 0xCA
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#define CXL_IOCTL_START_WORK _IOW(CXL_MAGIC, 0x00, struct cxl_ioctl_start_work)
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#define CXL_IOCTL_GET_PROCESS_ELEMENT _IOR(CXL_MAGIC, 0x01, __u32)
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#define CXL_IOCTL_GET_AFU_ID _IOR(CXL_MAGIC, 0x02, struct cxl_afu_id)
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#define CXL_READ_MIN_SIZE 0x1000 /* 4K */
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