mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-07-23 15:27:29 +00:00
Merge branch 'remotes/lorenzo/pci/dwc'
- Add Kirin MSI support (Xiaowei Song)
- Drop unnecessary root_bus_nr setting from exynos, imx6, keystone,
armada8k, artpec6, designware-plat, histb, qcom, spear13xx (Shawn Guo)
- Move link notification settings from DesignWare core to individual
drivers (Gustavo Pimentel)
- Add endpoint library MSI-X interfaces (Gustavo Pimentel)
- Correct signature of endpoint library IRQ interfaces (Gustavo Pimentel)
- Add DesignWare endpoint library MSI-X callbacks (Gustavo Pimentel)
- Add endpoint library MSI-X test support (Gustavo Pimentel)
* remotes/lorenzo/pci/dwc:
PCI: endpoint: Add MSI set maximum restriction
tools: PCI: Add MSI-X support
pci_endpoint_test: Add 2 ioctl commands
pci-epf-test/pci_endpoint_test: Add MSI-X support
pci-epf-test/pci_endpoint_test: Use irq_type module parameter
pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace
PCI: dwc: Add legacy interrupt callback handler
PCI: dwc: Rework MSI callbacks handler
PCI: dwc: Add MSI-X callbacks handler
PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures
PCI: endpoint: Add MSI-X interfaces
PCI: dwc: Fix EP link notification implementation
PCI: spear13xx: Drop unnecessary root_bus_nr setting
PCI: qcom: Drop unnecessary root_bus_nr setting
PCI: histb: Drop unnecessary root_bus_nr setting
PCI: designware-plat: Drop unnecessary root_bus_nr setting
PCI: artpec6: Drop unnecessary root_bus_nr setting
PCI: armada8k: Drop unnecessary root_bus_nr setting
PCI: keystone: Drop unnecessary root_bus_nr setting
PCI: imx6: Drop unnecessary root_bus_nr setting
PCI: exynos: Drop unnecessary root_bus_nr setting
PCI: kirin: Add MSI support
This commit is contained in:
Bjorn Helgaas
commit
0c38011aba
30 changed files with 759 additions and 155 deletions
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@ -370,7 +370,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
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}
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static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u8 interrupt_num)
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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@ -421,7 +421,6 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &exynos_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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@ -667,7 +667,6 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &imx6_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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@ -347,7 +347,6 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &keystone_pcie_host_ops;
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ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
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if (ret) {
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@ -172,7 +172,6 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
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struct device *dev = &pdev->dev;
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int ret;
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pp->root_bus_nr = -1;
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pp->ops = &armada8k_pcie_host_ops;
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pp->irq = platform_get_irq(pdev, 0);
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@ -399,7 +399,6 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &artpec6_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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@ -428,7 +427,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
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}
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static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u8 interrupt_num)
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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@ -40,6 +40,39 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
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__dw_pcie_ep_reset_bar(pci, bar, 0);
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}
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static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
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u8 cap)
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{
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u8 cap_id, next_cap_ptr;
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u16 reg;
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reg = dw_pcie_readw_dbi(pci, cap_ptr);
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next_cap_ptr = (reg & 0xff00) >> 8;
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cap_id = (reg & 0x00ff);
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if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
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return 0;
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if (cap_id == cap)
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return cap_ptr;
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return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
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}
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static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
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{
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u8 next_cap_ptr;
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u16 reg;
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reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
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next_cap_ptr = (reg & 0x00ff);
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if (!next_cap_ptr)
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return 0;
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return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
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}
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static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
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struct pci_epf_header *hdr)
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{
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@ -213,36 +246,84 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
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static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 val, reg;
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val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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if (!(val & MSI_CAP_MSI_EN_MASK))
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if (!ep->msi_cap)
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return -EINVAL;
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val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
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reg = ep->msi_cap + PCI_MSI_FLAGS;
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val = dw_pcie_readw_dbi(pci, reg);
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if (!(val & PCI_MSI_FLAGS_ENABLE))
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return -EINVAL;
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val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
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return val;
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}
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 val, reg;
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val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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val &= ~MSI_CAP_MMC_MASK;
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val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
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if (!ep->msi_cap)
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return -EINVAL;
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reg = ep->msi_cap + PCI_MSI_FLAGS;
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val = dw_pcie_readw_dbi(pci, reg);
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val &= ~PCI_MSI_FLAGS_QMASK;
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val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
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dw_pcie_writew_dbi(pci, reg, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 val, reg;
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if (!ep->msix_cap)
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return -EINVAL;
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reg = ep->msix_cap + PCI_MSIX_FLAGS;
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val = dw_pcie_readw_dbi(pci, reg);
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if (!(val & PCI_MSIX_FLAGS_ENABLE))
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return -EINVAL;
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val &= PCI_MSIX_FLAGS_QSIZE;
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return val;
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}
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static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 val, reg;
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if (!ep->msix_cap)
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return -EINVAL;
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reg = ep->msix_cap + PCI_MSIX_FLAGS;
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val = dw_pcie_readw_dbi(pci, reg);
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val &= ~PCI_MSIX_FLAGS_QSIZE;
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val |= interrupts;
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, reg, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
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enum pci_epc_irq_type type, u8 interrupt_num)
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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@ -282,32 +363,52 @@ static const struct pci_epc_ops epc_ops = {
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.unmap_addr = dw_pcie_ep_unmap_addr,
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.set_msi = dw_pcie_ep_set_msi,
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.get_msi = dw_pcie_ep_get_msi,
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.set_msix = dw_pcie_ep_set_msix,
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.get_msix = dw_pcie_ep_get_msix,
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.raise_irq = dw_pcie_ep_raise_irq,
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.start = dw_pcie_ep_start,
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.stop = dw_pcie_ep_stop,
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};
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int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct device *dev = pci->dev;
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dev_err(dev, "EP cannot trigger legacy IRQs\n");
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return -EINVAL;
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}
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int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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u8 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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u16 msg_ctrl, msg_data;
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u32 msg_addr_lower, msg_addr_upper;
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u32 msg_addr_lower, msg_addr_upper, reg;
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u64 msg_addr;
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bool has_upper;
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int ret;
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if (!ep->msi_cap)
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return -EINVAL;
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/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
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msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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reg = ep->msi_cap + PCI_MSI_FLAGS;
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msg_ctrl = dw_pcie_readw_dbi(pci, reg);
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has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
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msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
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reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
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msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
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if (has_upper) {
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msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
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msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
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reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
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msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
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reg = ep->msi_cap + PCI_MSI_DATA_64;
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msg_data = dw_pcie_readw_dbi(pci, reg);
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} else {
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msg_addr_upper = 0;
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msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
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reg = ep->msi_cap + PCI_MSI_DATA_32;
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msg_data = dw_pcie_readw_dbi(pci, reg);
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}
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msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
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ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
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@ -322,6 +423,64 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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return 0;
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}
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int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
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u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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u16 tbl_offset, bir;
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u32 bar_addr_upper, bar_addr_lower;
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u32 msg_addr_upper, msg_addr_lower;
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u32 reg, msg_data, vec_ctrl;
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u64 tbl_addr, msg_addr, reg_u64;
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void __iomem *msix_tbl;
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int ret;
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reg = ep->msix_cap + PCI_MSIX_TABLE;
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tbl_offset = dw_pcie_readl_dbi(pci, reg);
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bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
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tbl_offset &= PCI_MSIX_TABLE_OFFSET;
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tbl_offset >>= 3;
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reg = PCI_BASE_ADDRESS_0 + (4 * bir);
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bar_addr_upper = 0;
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bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
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reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
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if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
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bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
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tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
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tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
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tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
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msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
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PCI_MSIX_ENTRY_SIZE);
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if (!msix_tbl)
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return -EINVAL;
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msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
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msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
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msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
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msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
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vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
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iounmap(msix_tbl);
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if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
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return -EPERM;
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ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
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epc->mem->page_size);
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if (ret)
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return ret;
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writel(msg_data, ep->msi_mem);
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dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
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return 0;
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}
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void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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@ -386,15 +545,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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return -ENOMEM;
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ep->outbound_addr = addr;
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if (ep->ops->ep_init)
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ep->ops->ep_init(ep);
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epc = devm_pci_epc_create(dev, &epc_ops);
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if (IS_ERR(epc)) {
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dev_err(dev, "Failed to create epc device\n");
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return PTR_ERR(epc);
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}
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ep->epc = epc;
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epc_set_drvdata(epc, ep);
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if (ep->ops->ep_init)
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ep->ops->ep_init(ep);
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ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
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if (ret < 0)
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epc->max_functions = 1;
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@ -409,15 +571,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
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epc->mem->page_size);
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if (!ep->msi_mem) {
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dev_err(dev, "Failed to reserve memory for MSI\n");
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dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
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return -ENOMEM;
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}
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ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
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epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER;
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EPC_FEATURE_SET_BAR(epc->features, BAR_0);
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ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
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ep->epc = epc;
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epc_set_drvdata(epc, ep);
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dw_pcie_setup(pci);
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return 0;
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|
|
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@ -70,24 +70,29 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
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{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
struct pci_epc *epc = ep->epc;
|
||||
enum pci_barno bar;
|
||||
|
||||
for (bar = BAR_0; bar <= BAR_5; bar++)
|
||||
dw_pcie_ep_reset_bar(pci, bar);
|
||||
|
||||
epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
|
||||
epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
|
||||
}
|
||||
|
||||
static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type,
|
||||
u8 interrupt_num)
|
||||
u16 interrupt_num)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
|
||||
return -EINVAL;
|
||||
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
|
||||
case PCI_EPC_IRQ_MSIX:
|
||||
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
|
||||
default:
|
||||
dev_err(pci->dev, "UNKNOWN IRQ type\n");
|
||||
}
|
||||
|
|
@ -118,7 +123,6 @@ static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
|
|||
return pp->msi_irq;
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &dw_plat_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
|
|
|
|||
|
|
@ -96,17 +96,6 @@
|
|||
#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
|
||||
((0x3 << 20) | ((region) << 9) | (0x1 << 8))
|
||||
|
||||
#define MSI_MESSAGE_CONTROL 0x52
|
||||
#define MSI_CAP_MMC_SHIFT 1
|
||||
#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
|
||||
#define MSI_CAP_MME_SHIFT 4
|
||||
#define MSI_CAP_MSI_EN_MASK 0x1
|
||||
#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
|
||||
#define MSI_MESSAGE_ADDR_L32 0x54
|
||||
#define MSI_MESSAGE_ADDR_U32 0x58
|
||||
#define MSI_MESSAGE_DATA_32 0x58
|
||||
#define MSI_MESSAGE_DATA_64 0x5C
|
||||
|
||||
#define MAX_MSI_IRQS 256
|
||||
#define MAX_MSI_IRQS_PER_CTRL 32
|
||||
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
|
||||
|
|
@ -191,7 +180,7 @@ enum dw_pcie_as_type {
|
|||
struct dw_pcie_ep_ops {
|
||||
void (*ep_init)(struct dw_pcie_ep *ep);
|
||||
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type, u8 interrupt_num);
|
||||
enum pci_epc_irq_type type, u16 interrupt_num);
|
||||
};
|
||||
|
||||
struct dw_pcie_ep {
|
||||
|
|
@ -208,6 +197,8 @@ struct dw_pcie_ep {
|
|||
u32 num_ob_windows;
|
||||
void __iomem *msi_mem;
|
||||
phys_addr_t msi_mem_phys;
|
||||
u8 msi_cap; /* MSI capability offset */
|
||||
u8 msix_cap; /* MSI-X capability offset */
|
||||
};
|
||||
|
||||
struct dw_pcie_ops {
|
||||
|
|
@ -357,8 +348,11 @@ static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
|
|||
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
|
||||
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
|
||||
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
|
||||
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
|
||||
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
u8 interrupt_num);
|
||||
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
u16 interrupt_num);
|
||||
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
|
||||
#else
|
||||
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
|
||||
|
|
@ -374,12 +368,23 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
|||
{
|
||||
}
|
||||
|
||||
static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
u8 interrupt_num)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
u16 interrupt_num)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -420,7 +420,6 @@ static int histb_pcie_probe(struct platform_device *pdev)
|
|||
phy_init(hipcie->phy);
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &histb_pcie_host_ops;
|
||||
|
||||
platform_set_drvdata(pdev, hipcie);
|
||||
|
|
|
|||
|
|
@ -430,6 +430,9 @@ static int kirin_pcie_host_init(struct pcie_port *pp)
|
|||
{
|
||||
kirin_pcie_establish_link(pp);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
dw_pcie_msi_init(pp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -445,9 +448,34 @@ static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
|
|||
.host_init = kirin_pcie_host_init,
|
||||
};
|
||||
|
||||
static int kirin_pcie_add_msi(struct dw_pcie *pci,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get MSI IRQ (%d)\n", irq);
|
||||
return irq;
|
||||
}
|
||||
|
||||
pci->pp.msi_irq = irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init kirin_add_pcie_port(struct dw_pcie *pci,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = kirin_pcie_add_msi(pci, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pci->pp.ops = &kirin_pcie_host_ops;
|
||||
|
||||
return dw_pcie_host_init(&pci->pp);
|
||||
|
|
|
|||
|
|
@ -1251,7 +1251,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &qcom_pcie_dw_ops;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
|
|
|
|||
|
|
@ -210,7 +210,6 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
|
|||
return ret;
|
||||
}
|
||||
|
||||
pp->root_bus_nr = -1;
|
||||
pp->ops = &spear13xx_pcie_host_ops;
|
||||
|
||||
ret = dw_pcie_host_init(pp);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue