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ARM: KVM: invalidate icache on guest exit for Cortex-A15
In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com>
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2 changed files with 29 additions and 0 deletions
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@ -306,6 +306,11 @@ static inline void *kvm_get_hyp_vector(void)
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return kvm_ksym_ref(__kvm_hyp_vector_bp_inv);
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return kvm_ksym_ref(__kvm_hyp_vector_bp_inv);
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}
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}
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case ARM_CPU_PART_CORTEX_A15:
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{
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extern char __kvm_hyp_vector_ic_inv[];
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return kvm_ksym_ref(__kvm_hyp_vector_ic_inv);
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}
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#endif
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#endif
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default:
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default:
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{
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{
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@ -72,6 +72,28 @@ __kvm_hyp_vector:
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W(b) hyp_fiq
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W(b) hyp_fiq
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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.align 5
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__kvm_hyp_vector_ic_inv:
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.global __kvm_hyp_vector_ic_inv
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/*
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* We encode the exception entry in the bottom 3 bits of
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* SP, and we have to guarantee to be 8 bytes aligned.
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*/
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W(add) sp, sp, #1 /* Reset 7 */
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W(add) sp, sp, #1 /* Undef 6 */
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W(add) sp, sp, #1 /* Syscall 5 */
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W(add) sp, sp, #1 /* Prefetch abort 4 */
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W(add) sp, sp, #1 /* Data abort 3 */
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W(add) sp, sp, #1 /* HVC 2 */
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W(add) sp, sp, #1 /* IRQ 1 */
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W(nop) /* FIQ 0 */
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mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
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isb
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b decode_vectors
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.align 5
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.align 5
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__kvm_hyp_vector_bp_inv:
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__kvm_hyp_vector_bp_inv:
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.global __kvm_hyp_vector_bp_inv
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.global __kvm_hyp_vector_bp_inv
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@ -92,6 +114,8 @@ __kvm_hyp_vector_bp_inv:
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
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isb
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isb
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decode_vectors:
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#ifdef CONFIG_THUMB2_KERNEL
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#ifdef CONFIG_THUMB2_KERNEL
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/*
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/*
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* Yet another silly hack: Use VPIDR as a temp register.
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* Yet another silly hack: Use VPIDR as a temp register.
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