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drm/amdgpu: add vcn enc rings
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
3639f7d855
commit
101c6fee53
3 changed files with 33 additions and 2 deletions
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@ -126,6 +126,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
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{
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{
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int i;
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kfree(adev->vcn.saved_bo);
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kfree(adev->vcn.saved_bo);
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amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
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amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
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@ -138,6 +140,9 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
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amdgpu_ring_fini(&adev->vcn.ring_dec);
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amdgpu_ring_fini(&adev->vcn.ring_dec);
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for (i = 0; i < adev->vcn.num_enc_rings; ++i)
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amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
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release_firmware(adev->vcn.fw);
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release_firmware(adev->vcn.fw);
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return 0;
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return 0;
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@ -50,7 +50,7 @@ struct amdgpu_vcn {
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struct amdgpu_irq_src irq;
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struct amdgpu_irq_src irq;
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struct amd_sched_entity entity_dec;
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struct amd_sched_entity entity_dec;
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struct amd_sched_entity entity_enc;
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struct amd_sched_entity entity_enc;
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uint32_t srbm_soft_reset;
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unsigned num_enc_rings;
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};
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};
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
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@ -51,6 +51,8 @@ static int vcn_v1_0_early_init(void *handle)
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{
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->vcn.num_enc_rings = 2;
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vcn_v1_0_set_dec_ring_funcs(adev);
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vcn_v1_0_set_dec_ring_funcs(adev);
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vcn_v1_0_set_irq_funcs(adev);
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vcn_v1_0_set_irq_funcs(adev);
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@ -67,7 +69,7 @@ static int vcn_v1_0_early_init(void *handle)
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static int vcn_v1_0_sw_init(void *handle)
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static int vcn_v1_0_sw_init(void *handle)
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{
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{
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struct amdgpu_ring *ring;
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struct amdgpu_ring *ring;
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int r;
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int i, r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* VCN TRAP */
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/* VCN TRAP */
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@ -86,6 +88,16 @@ static int vcn_v1_0_sw_init(void *handle)
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ring = &adev->vcn.ring_dec;
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ring = &adev->vcn.ring_dec;
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sprintf(ring->name, "vcn_dec");
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sprintf(ring->name, "vcn_dec");
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r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
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r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
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if (r)
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return r;
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for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
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ring = &adev->vcn.ring_enc[i];
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sprintf(ring->name, "vcn_enc%d", i);
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r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
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if (r)
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return r;
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}
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return r;
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return r;
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}
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}
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@ -401,6 +413,20 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
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~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
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~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
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ring = &adev->vcn.ring_enc[0];
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
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ring = &adev->vcn.ring_enc[1];
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
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return 0;
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return 0;
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}
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}
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