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https://github.com/Fishwaldo/Star64_linux.git
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drm/amdgpu: Delete some cgs functions
Drop cgs wrappers that are no longer used. 1. cgs_rel_firmwar 2. cgs_is_virtualization_enabled 3. cgs_notify_dpm_enabled 4. cgs_atom_get_data_table 5. cgs_atom_get_cmd_table_revs 6. cgs_atom_exec_cmd_table 7. cgs_get_active_displays_info Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
555fd70c59
commit
10b3f45c4a
2 changed files with 0 additions and 336 deletions
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@ -23,7 +23,6 @@
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <drm/drmP.h>
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#include <linux/firmware.h>
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#include <drm/amdgpu_drm.h>
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@ -109,78 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
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WARN(1, "Invalid indirect register space");
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}
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static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
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enum cgs_resource_type resource_type,
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uint64_t size,
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uint64_t offset,
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uint64_t *resource_base)
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{
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CGS_FUNC_ADEV;
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if (resource_base == NULL)
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return -EINVAL;
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switch (resource_type) {
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case CGS_RESOURCE_TYPE_MMIO:
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if (adev->rmmio_size == 0)
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return -ENOENT;
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if ((offset + size) > adev->rmmio_size)
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return -EINVAL;
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*resource_base = adev->rmmio_base;
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return 0;
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case CGS_RESOURCE_TYPE_DOORBELL:
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if (adev->doorbell.size == 0)
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return -ENOENT;
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if ((offset + size) > adev->doorbell.size)
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return -EINVAL;
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*resource_base = adev->doorbell.base;
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return 0;
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case CGS_RESOURCE_TYPE_FB:
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case CGS_RESOURCE_TYPE_IO:
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case CGS_RESOURCE_TYPE_ROM:
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default:
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return -EINVAL;
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}
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}
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static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
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unsigned table, uint16_t *size,
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uint8_t *frev, uint8_t *crev)
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{
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CGS_FUNC_ADEV;
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uint16_t data_start;
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if (amdgpu_atom_parse_data_header(
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adev->mode_info.atom_context, table, size,
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frev, crev, &data_start))
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return (uint8_t*)adev->mode_info.atom_context->bios +
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data_start;
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return NULL;
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}
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static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
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uint8_t *frev, uint8_t *crev)
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{
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CGS_FUNC_ADEV;
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if (amdgpu_atom_parse_cmd_header(
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adev->mode_info.atom_context, table,
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frev, crev))
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return 0;
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return -EINVAL;
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}
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static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
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void *args)
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{
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CGS_FUNC_ADEV;
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return amdgpu_atom_execute_table(
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adev->mode_info.atom_context, table, args);
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}
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static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state)
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@ -223,7 +150,6 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
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return r;
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}
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static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
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{
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CGS_FUNC_ADEV;
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@ -271,18 +197,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
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return result;
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}
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static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
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{
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CGS_FUNC_ADEV;
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if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
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release_firmware(adev->pm.fw);
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adev->pm.fw = NULL;
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return 0;
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}
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/* cannot release other firmware because they are not created by cgs */
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return -EINVAL;
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}
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static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
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enum cgs_ucode_id type)
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{
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@ -326,34 +240,6 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
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return fw_version;
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}
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static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
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bool en)
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{
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CGS_FUNC_ADEV;
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if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
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adev->gfx.rlc.funcs->exit_safe_mode == NULL)
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return 0;
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if (en)
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adev->gfx.rlc.funcs->enter_safe_mode(adev);
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else
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adev->gfx.rlc.funcs->exit_safe_mode(adev);
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return 0;
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}
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static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
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bool lock)
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{
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CGS_FUNC_ADEV;
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if (lock)
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mutex_lock(&adev->grbm_idx_mutex);
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else
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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enum cgs_ucode_id type,
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struct cgs_firmware_info *info)
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@ -598,97 +484,14 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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return 0;
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}
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static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
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{
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CGS_FUNC_ADEV;
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return amdgpu_sriov_vf(adev);
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}
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static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
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struct cgs_display_info *info)
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{
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CGS_FUNC_ADEV;
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struct cgs_mode_info *mode_info;
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if (info == NULL)
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return -EINVAL;
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mode_info = info->mode_info;
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if (mode_info)
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/* if the displays are off, vblank time is max */
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mode_info->vblank_time_us = 0xffffffff;
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if (!amdgpu_device_has_dc_support(adev)) {
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struct amdgpu_crtc *amdgpu_crtc;
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struct drm_device *ddev = adev->ddev;
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struct drm_crtc *crtc;
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uint32_t line_time_us, vblank_lines;
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if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
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list_for_each_entry(crtc,
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&ddev->mode_config.crtc_list, head) {
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amdgpu_crtc = to_amdgpu_crtc(crtc);
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if (crtc->enabled) {
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info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
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info->display_count++;
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}
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if (mode_info != NULL &&
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crtc->enabled && amdgpu_crtc->enabled &&
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amdgpu_crtc->hw_mode.clock) {
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line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
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amdgpu_crtc->hw_mode.clock;
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vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
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amdgpu_crtc->hw_mode.crtc_vdisplay +
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(amdgpu_crtc->v_border * 2);
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mode_info->vblank_time_us = vblank_lines * line_time_us;
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mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
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/* we have issues with mclk switching with refresh rates
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* over 120 hz on the non-DC code.
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*/
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if (mode_info->refresh_rate > 120)
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mode_info->vblank_time_us = 0;
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mode_info = NULL;
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}
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}
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}
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} else {
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info->display_count = adev->pm.pm_display_cfg.num_display;
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if (mode_info != NULL) {
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mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
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mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
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}
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}
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return 0;
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}
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static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
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{
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CGS_FUNC_ADEV;
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adev->pm.dpm_enabled = enabled;
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return 0;
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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.read_register = amdgpu_cgs_read_register,
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.write_register = amdgpu_cgs_write_register,
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.read_ind_register = amdgpu_cgs_read_ind_register,
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.write_ind_register = amdgpu_cgs_write_ind_register,
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.get_pci_resource = amdgpu_cgs_get_pci_resource,
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.atom_get_data_table = amdgpu_cgs_atom_get_data_table,
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.atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
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.atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
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.get_firmware_info = amdgpu_cgs_get_firmware_info,
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.rel_firmware = amdgpu_cgs_rel_firmware,
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.set_powergating_state = amdgpu_cgs_set_powergating_state,
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.set_clockgating_state = amdgpu_cgs_set_clockgating_state,
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.get_active_displays_info = amdgpu_cgs_get_active_displays_info,
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.notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
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.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
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.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
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.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
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};
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struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
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@ -76,17 +76,6 @@ enum cgs_ucode_id {
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CGS_UCODE_ID_MAXIMUM,
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};
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/*
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* enum cgs_resource_type - GPU resource type
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*/
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enum cgs_resource_type {
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CGS_RESOURCE_TYPE_MMIO = 0,
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CGS_RESOURCE_TYPE_FB,
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CGS_RESOURCE_TYPE_IO,
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CGS_RESOURCE_TYPE_DOORBELL,
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CGS_RESOURCE_TYPE_ROM,
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};
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/**
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* struct cgs_firmware_info - Firmware information
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*/
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@ -104,17 +93,6 @@ struct cgs_firmware_info {
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bool is_kicker;
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};
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struct cgs_mode_info {
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uint32_t refresh_rate;
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uint32_t vblank_time_us;
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};
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struct cgs_display_info {
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uint32_t display_count;
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uint32_t active_display_mask;
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struct cgs_mode_info *mode_info;
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};
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typedef unsigned long cgs_handle_t;
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/**
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@ -170,73 +148,10 @@ typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs
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#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
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cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
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/**
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* cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
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* @cgs_device: opaque device handle
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* @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
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* @size: size of the region
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* @offset: offset from the start of the region
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* @resource_base: base address (not including offset) returned
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
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enum cgs_resource_type resource_type,
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uint64_t size,
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uint64_t offset,
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uint64_t *resource_base);
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/**
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* cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
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* @cgs_device: opaque device handle
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* @table: data table index
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* @size: size of the table (output, may be NULL)
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: Pointer to start of the table, or NULL on failure
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*/
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typedef const void *(*cgs_atom_get_data_table_t)(
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struct cgs_device *cgs_device, unsigned table,
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uint16_t *size, uint8_t *frev, uint8_t *crev);
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/**
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* cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
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* @cgs_device: opaque device handle
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* @table: data table index
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
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uint8_t *frev, uint8_t *crev);
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/**
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* cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
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* @cgs_device: opaque device handle
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* @table: command table index
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* @args: arguments
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
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unsigned table, void *args);
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/**
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* cgs_get_firmware_info - Get the firmware information from core driver
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* @cgs_device: opaque device handle
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* @type: the firmware type
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* @info: returend firmware information
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
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enum cgs_ucode_id type,
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struct cgs_firmware_info *info);
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typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
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enum cgs_ucode_id type);
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typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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@ -246,43 +161,17 @@ typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state);
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typedef int(*cgs_get_active_displays_info)(
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struct cgs_device *cgs_device,
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struct cgs_display_info *info);
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typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
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typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
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typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
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typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
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struct cgs_ops {
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/* MMIO access */
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cgs_read_register_t read_register;
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cgs_write_register_t write_register;
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cgs_read_ind_register_t read_ind_register;
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cgs_write_ind_register_t write_ind_register;
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/* PCI resources */
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cgs_get_pci_resource_t get_pci_resource;
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/* ATOM BIOS */
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cgs_atom_get_data_table_t atom_get_data_table;
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cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
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cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
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/* Firmware Info */
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cgs_get_firmware_info get_firmware_info;
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cgs_rel_firmware rel_firmware;
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/* cg pg interface*/
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cgs_set_powergating_state set_powergating_state;
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cgs_set_clockgating_state set_clockgating_state;
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/* display manager */
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cgs_get_active_displays_info get_active_displays_info;
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/* notify dpm enabled */
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cgs_notify_dpm_enabled notify_dpm_enabled;
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cgs_is_virtualization_enabled_t is_virtualization_enabled;
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cgs_enter_safe_mode enter_safe_mode;
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cgs_lock_grbm_idx lock_grbm_idx;
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};
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struct cgs_os_ops; /* To be define in OS-specific CGS header */
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@ -309,40 +198,12 @@ struct cgs_device
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#define cgs_write_ind_register(dev,space,index,value) \
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CGS_CALL(write_ind_register,dev,space,index,value)
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#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
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CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
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#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
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CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
|
||||
#define cgs_atom_exec_cmd_table(dev,table,args) \
|
||||
CGS_CALL(atom_exec_cmd_table,dev,table,args)
|
||||
|
||||
#define cgs_get_firmware_info(dev, type, info) \
|
||||
CGS_CALL(get_firmware_info, dev, type, info)
|
||||
#define cgs_rel_firmware(dev, type) \
|
||||
CGS_CALL(rel_firmware, dev, type)
|
||||
#define cgs_set_powergating_state(dev, block_type, state) \
|
||||
CGS_CALL(set_powergating_state, dev, block_type, state)
|
||||
#define cgs_set_clockgating_state(dev, block_type, state) \
|
||||
CGS_CALL(set_clockgating_state, dev, block_type, state)
|
||||
#define cgs_notify_dpm_enabled(dev, enabled) \
|
||||
CGS_CALL(notify_dpm_enabled, dev, enabled)
|
||||
|
||||
#define cgs_get_active_displays_info(dev, info) \
|
||||
CGS_CALL(get_active_displays_info, dev, info)
|
||||
|
||||
#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
|
||||
resource_base) \
|
||||
CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
|
||||
resource_base)
|
||||
|
||||
#define cgs_is_virtualization_enabled(cgs_device) \
|
||||
CGS_CALL(is_virtualization_enabled, cgs_device)
|
||||
|
||||
#define cgs_enter_safe_mode(cgs_device, en) \
|
||||
CGS_CALL(enter_safe_mode, cgs_device, en)
|
||||
|
||||
#define cgs_lock_grbm_idx(cgs_device, lock) \
|
||||
CGS_CALL(lock_grbm_idx, cgs_device, lock)
|
||||
|
||||
|
||||
#endif /* _CGS_COMMON_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue