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Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"

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This reverts commit 444a0fea51.

We are ready to enable it now.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Thong Thai 2019-08-22 17:42:53 -05:00 • committed by Alex Deucher
parent f13580a947
commit 134b1461ea
2 changed files with 6 additions and 12 deletions
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9
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View file

@ -100,8 +100,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
case CHIP_NAVI14:
fw_name = FIRMWARE_NAVI14;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
case CHIP_NAVI12:
@ -161,8 +160,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
adev->asic_type == CHIP_RENOIR)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@ -273,8 +271,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
unsigned offset;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
adev->asic_type == CHIP_RENOIR) {
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
le32_to_cpu(hdr->ucode_size_bytes));

9
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View file

@ -142,8 +142,7 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
const struct common_firmware_header *hdr;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
@ -367,8 +366,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
uint32_t offset;
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@ -413,8 +411,7 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
uint32_t offset;
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),