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drm/amdgpu: Remove wrapper layer of cgs irq handling
v2: add Vega12 support 1. remove struct cgs_os_ops 2. delete cgs_linux.h 3. refine the irq code for vega10, can fix set pp table failed issue. 4. add common smu irq process function Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7436854ebd
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160b8e7593
11 changed files with 86 additions and 364 deletions
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@ -28,7 +28,6 @@
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#include <linux/firmware.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "cgs_linux.h"
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#include "atom.h"
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#include "amdgpu_ucode.h"
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@ -182,109 +181,6 @@ static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigne
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adev->mode_info.atom_context, table, args);
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}
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struct cgs_irq_params {
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unsigned src_id;
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cgs_irq_source_set_func_t set;
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cgs_irq_handler_func_t handler;
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void *private_data;
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};
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static int cgs_set_irq_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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struct cgs_irq_params *irq_params =
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(struct cgs_irq_params *)src->data;
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if (!irq_params)
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return -EINVAL;
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if (!irq_params->set)
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return -EINVAL;
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return irq_params->set(irq_params->private_data,
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irq_params->src_id,
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type,
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(int)state);
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}
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static int cgs_process_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct cgs_irq_params *irq_params =
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(struct cgs_irq_params *)source->data;
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if (!irq_params)
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return -EINVAL;
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if (!irq_params->handler)
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return -EINVAL;
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return irq_params->handler(irq_params->private_data,
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irq_params->src_id,
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entry->iv_entry);
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}
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static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
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.set = cgs_set_irq_state,
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.process = cgs_process_irq,
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};
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static int amdgpu_cgs_add_irq_source(void *cgs_device,
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unsigned client_id,
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unsigned src_id,
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unsigned num_types,
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cgs_irq_source_set_func_t set,
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cgs_irq_handler_func_t handler,
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void *private_data)
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{
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CGS_FUNC_ADEV;
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int ret = 0;
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struct cgs_irq_params *irq_params;
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struct amdgpu_irq_src *source =
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kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
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if (!source)
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return -ENOMEM;
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irq_params =
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kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
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if (!irq_params) {
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kfree(source);
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return -ENOMEM;
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}
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source->num_types = num_types;
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source->funcs = &cgs_irq_funcs;
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irq_params->src_id = src_id;
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irq_params->set = set;
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irq_params->handler = handler;
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irq_params->private_data = private_data;
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source->data = (void *)irq_params;
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ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
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if (ret) {
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kfree(irq_params);
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kfree(source);
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}
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return ret;
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}
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static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
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unsigned src_id, unsigned type)
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{
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CGS_FUNC_ADEV;
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if (!adev->irq.client[client_id].sources)
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return -EINVAL;
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return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
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}
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static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
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unsigned src_id, unsigned type)
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{
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CGS_FUNC_ADEV;
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if (!adev->irq.client[client_id].sources)
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return -EINVAL;
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return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
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}
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static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state)
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@ -795,12 +691,6 @@ static const struct cgs_ops amdgpu_cgs_ops = {
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.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
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};
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static const struct cgs_os_ops amdgpu_cgs_os_ops = {
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.add_irq_source = amdgpu_cgs_add_irq_source,
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.irq_get = amdgpu_cgs_irq_get,
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.irq_put = amdgpu_cgs_irq_put
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};
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struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
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{
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struct amdgpu_cgs_device *cgs_device =
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@ -812,7 +702,6 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
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}
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cgs_device->base.ops = &amdgpu_cgs_ops;
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cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
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cgs_device->adev = adev;
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return (struct cgs_device *)cgs_device;
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