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https://github.com/Fishwaldo/Star64_linux.git
synced 2025-07-06 14:31:46 +00:00
accel/ivpu: Refactor memory ranges logic
Add new dma range and change naming convention for virtual address memory ranges managed by KMD. New available ranges are named as follows: * global range - global context accessible by FW * aliased range - user context accessible by FW * dma range - user context accessible by DMA * shave range - user context accessible by shaves * global shave range - global context accessible by shave nn Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230731161258.2987564-6-stanislaw.gruszka@linux.intel.com
This commit is contained in:
parent
aa5f04d2e5
commit
162f17b2d9
7 changed files with 32 additions and 31 deletions
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@ -122,7 +122,7 @@ static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param
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args->value = 0;
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args->value = 0;
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break;
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break;
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case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
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case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
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args->value = 0;
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args->value = 1;
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break;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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@ -160,7 +160,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f
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args->value = ivpu_get_context_count(vdev);
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args->value = ivpu_get_context_count(vdev);
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break;
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break;
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case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
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case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
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args->value = vdev->hw->ranges.user_low.start;
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args->value = vdev->hw->ranges.user.start;
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break;
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break;
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case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
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case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
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args->value = file_priv->priority;
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args->value = file_priv->priority;
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@ -204,7 +204,7 @@ static int ivpu_fw_update_global_range(struct ivpu_device *vdev)
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return -EINVAL;
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return -EINVAL;
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}
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}
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ivpu_hw_init_range(&vdev->hw->ranges.global_low, start, size);
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ivpu_hw_init_range(&vdev->hw->ranges.global, start, size);
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return 0;
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return 0;
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}
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}
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@ -245,7 +245,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev)
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}
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}
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if (fw->shave_nn_size) {
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if (fw->shave_nn_size) {
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fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.global_high.start,
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fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.shave.start,
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fw->shave_nn_size, DRM_IVPU_BO_UNCACHED);
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fw->shave_nn_size, DRM_IVPU_BO_UNCACHED);
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if (!fw->mem_shave_nn) {
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if (!fw->mem_shave_nn) {
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ivpu_err(vdev, "Failed to allocate shavenn buffer\n");
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ivpu_err(vdev, "Failed to allocate shavenn buffer\n");
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@ -443,9 +443,9 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
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* Uncached region of VPU address space, covers IPC buffers, job queues
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* Uncached region of VPU address space, covers IPC buffers, job queues
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* and log buffers, programmable to L2$ Uncached by VPU MTRR
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* and log buffers, programmable to L2$ Uncached by VPU MTRR
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*/
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*/
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boot_params->shared_region_base = vdev->hw->ranges.global_low.start;
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boot_params->shared_region_base = vdev->hw->ranges.global.start;
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boot_params->shared_region_size = vdev->hw->ranges.global_low.end -
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boot_params->shared_region_size = vdev->hw->ranges.global.end -
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vdev->hw->ranges.global_low.start;
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vdev->hw->ranges.global.start;
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boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
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boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
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boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2;
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boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2;
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@ -453,10 +453,8 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
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boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2;
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boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2;
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boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2;
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boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2;
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boot_params->global_aliased_pio_base =
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boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
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vdev->hw->ranges.global_aliased_pio.start;
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boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
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boot_params->global_aliased_pio_size =
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ivpu_hw_range_size(&vdev->hw->ranges.global_aliased_pio);
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/* Allow configuration for L2C_PAGE_TABLE with boot param value */
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/* Allow configuration for L2C_PAGE_TABLE with boot param value */
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boot_params->autoconfig = 1;
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boot_params->autoconfig = 1;
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@ -464,7 +462,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
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/* Enable L2 cache for first 2GB of high memory */
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/* Enable L2 cache for first 2GB of high memory */
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boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
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boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
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boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
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boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
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ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.global_high.start);
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ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
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if (vdev->fw->mem_shave_nn)
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if (vdev->fw->mem_shave_nn)
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boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
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boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;
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@ -279,10 +279,12 @@ ivpu_bo_alloc_vpu_addr(struct ivpu_bo *bo, struct ivpu_mmu_context *ctx,
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int ret;
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int ret;
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if (!range) {
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if (!range) {
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if (bo->flags & DRM_IVPU_BO_HIGH_MEM)
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if (bo->flags & DRM_IVPU_BO_SHAVE_MEM)
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range = &vdev->hw->ranges.user_high;
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range = &vdev->hw->ranges.shave;
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else if (bo->flags & DRM_IVPU_BO_DMA_MEM)
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range = &vdev->hw->ranges.dma;
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else
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else
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range = &vdev->hw->ranges.user_low;
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range = &vdev->hw->ranges.user;
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}
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}
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mutex_lock(&ctx->lock);
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mutex_lock(&ctx->lock);
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@ -570,7 +572,7 @@ ivpu_bo_alloc_internal(struct ivpu_device *vdev, u64 vpu_addr, u64 size, u32 fla
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fixed_range.end = vpu_addr + size;
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fixed_range.end = vpu_addr + size;
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range = &fixed_range;
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range = &fixed_range;
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} else {
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} else {
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range = &vdev->hw->ranges.global_low;
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range = &vdev->hw->ranges.global;
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}
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}
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bo = ivpu_bo_alloc(vdev, &vdev->gctx, size, flags, &internal_ops, range, 0);
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bo = ivpu_bo_alloc(vdev, &vdev->gctx, size, flags, &internal_ops, range, 0);
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@ -38,11 +38,10 @@ struct ivpu_addr_range {
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struct ivpu_hw_info {
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struct ivpu_hw_info {
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const struct ivpu_hw_ops *ops;
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const struct ivpu_hw_ops *ops;
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struct {
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struct {
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struct ivpu_addr_range global_low;
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struct ivpu_addr_range global;
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struct ivpu_addr_range global_high;
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struct ivpu_addr_range user;
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struct ivpu_addr_range user_low;
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struct ivpu_addr_range shave;
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struct ivpu_addr_range user_high;
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struct ivpu_addr_range dma;
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struct ivpu_addr_range global_aliased_pio;
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} ranges;
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} ranges;
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struct {
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struct {
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u8 min_ratio;
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u8 min_ratio;
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@ -620,11 +620,10 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
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ivpu_pll_init_frequency_ratios(vdev);
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ivpu_pll_init_frequency_ratios(vdev);
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ivpu_hw_init_range(&hw->ranges.global_low, 0x80000000, SZ_512M);
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ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M);
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ivpu_hw_init_range(&hw->ranges.global_high, 0x180000000, SZ_2M);
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ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M);
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ivpu_hw_init_range(&hw->ranges.user_low, 0xc0000000, 255 * SZ_1M);
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ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G);
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ivpu_hw_init_range(&hw->ranges.user_high, 0x180000000, SZ_2G);
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ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G);
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hw->ranges.global_aliased_pio = hw->ranges.user_low;
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return 0;
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return 0;
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}
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}
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@ -431,11 +431,11 @@ ivpu_mmu_context_init(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u3
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return ret;
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return ret;
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if (!context_id) {
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if (!context_id) {
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start = vdev->hw->ranges.global_low.start;
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start = vdev->hw->ranges.global.start;
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end = vdev->hw->ranges.global_high.end;
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end = vdev->hw->ranges.shave.end;
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} else {
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} else {
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start = vdev->hw->ranges.user_low.start;
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start = vdev->hw->ranges.user.start;
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end = vdev->hw->ranges.user_high.end;
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end = vdev->hw->ranges.dma.end;
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}
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}
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drm_mm_init(&ctx->mm, start, end - start);
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drm_mm_init(&ctx->mm, start, end - start);
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@ -133,8 +133,10 @@ struct drm_ivpu_param {
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__u64 value;
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__u64 value;
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};
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};
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#define DRM_IVPU_BO_HIGH_MEM 0x00000001
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#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
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#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
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#define DRM_IVPU_BO_MAPPABLE 0x00000002
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#define DRM_IVPU_BO_MAPPABLE 0x00000002
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#define DRM_IVPU_BO_DMA_MEM 0x00000004
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#define DRM_IVPU_BO_CACHED 0x00000000
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#define DRM_IVPU_BO_CACHED 0x00000000
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#define DRM_IVPU_BO_UNCACHED 0x00010000
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#define DRM_IVPU_BO_UNCACHED 0x00010000
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@ -144,6 +146,7 @@ struct drm_ivpu_param {
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#define DRM_IVPU_BO_FLAGS \
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#define DRM_IVPU_BO_FLAGS \
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(DRM_IVPU_BO_HIGH_MEM | \
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(DRM_IVPU_BO_HIGH_MEM | \
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DRM_IVPU_BO_MAPPABLE | \
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DRM_IVPU_BO_MAPPABLE | \
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DRM_IVPU_BO_DMA_MEM | \
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DRM_IVPU_BO_CACHE_MASK)
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DRM_IVPU_BO_CACHE_MASK)
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/**
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/**
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