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drm/i915/display/psr: Make WARN* drm specific where drm_priv ptr is available

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drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.

The conversion was done automatically with below coccinelle semantic
patch.

@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}

Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200128181603.27767-17-pankaj.laxminarayan.bharadiya@intel.com
This commit is contained in:
Pankaj Bharadiya 2020-01-28 23:45:58 +05:30 • committed by Jani Nikula
parent 48522d3eed
commit 16c56083c0
1 changed files with 17 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

32
drivers/gpu/drm/i915/display/intel_psr.c
View file

@ -77,8 +77,8 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state) const struct intel_crtc_state *crtc_state)
{ {
/* Cannot enable DSC and PSR2 simultaneously */ /* Cannot enable DSC and PSR2 simultaneously */
WARN_ON(crtc_state->dsc.compression_enable && drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
crtc_state->has_psr2); crtc_state->has_psr2);
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE: case I915_PSR_DEBUG_DISABLE:
@ -469,7 +469,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
idle_frames = max(6, dev_priv->vbt.psr.idle_frames); idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
if (WARN_ON(idle_frames > 0xf)) if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
idle_frames = 0xf; idle_frames = 0xf;
return idle_frames; return idle_frames;
@ -628,7 +628,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
exit_scanlines = exit_scanlines =
intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
if (WARN_ON(exit_scanlines > crtc_vdisplay)) if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
return; return;
crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
@ -768,10 +768,12 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
WARN_ON(intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); drm_WARN_ON(&dev_priv->drm,
intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
WARN_ON(intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); drm_WARN_ON(&dev_priv->drm,
WARN_ON(dev_priv->psr.active); intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
lockdep_assert_held(&dev_priv->psr.lock); lockdep_assert_held(&dev_priv->psr.lock);
/* psr1 and psr2 are mutually exclusive.*/ /* psr1 and psr2 are mutually exclusive.*/
@ -846,7 +848,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
struct intel_dp *intel_dp = dev_priv->psr.dp; struct intel_dp *intel_dp = dev_priv->psr.dp;
u32 val; u32 val;
WARN_ON(dev_priv->psr.enabled); drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.busy_frontbuffer_bits = 0;
@ -904,10 +906,10 @@ void intel_psr_enable(struct intel_dp *intel_dp,
if (!crtc_state->has_psr) if (!crtc_state->has_psr)
return; return;
if (WARN_ON(!CAN_PSR(dev_priv))) if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
return; return;
WARN_ON(dev_priv->drrs.dp); drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock); mutex_lock(&dev_priv->psr.lock);
@ -930,12 +932,12 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
val = intel_de_read(dev_priv, val = intel_de_read(dev_priv,
EDP_PSR2_CTL(dev_priv->psr.transcoder)); EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(val & EDP_PSR2_ENABLE); drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
} }
val = intel_de_read(dev_priv, val = intel_de_read(dev_priv,
EDP_PSR_CTL(dev_priv->psr.transcoder)); EDP_PSR_CTL(dev_priv->psr.transcoder));
WARN_ON(val & EDP_PSR_ENABLE); drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
return; return;
} }
@ -944,14 +946,14 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
tgl_disallow_dc3co_on_psr2_exit(dev_priv); tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = intel_de_read(dev_priv, val = intel_de_read(dev_priv,
EDP_PSR2_CTL(dev_priv->psr.transcoder)); EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR2_ENABLE)); drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
val &= ~EDP_PSR2_ENABLE; val &= ~EDP_PSR2_ENABLE;
intel_de_write(dev_priv, intel_de_write(dev_priv,
EDP_PSR2_CTL(dev_priv->psr.transcoder), val); EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
} else { } else {
val = intel_de_read(dev_priv, val = intel_de_read(dev_priv,
EDP_PSR_CTL(dev_priv->psr.transcoder)); EDP_PSR_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR_ENABLE)); drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
val &= ~EDP_PSR_ENABLE; val &= ~EDP_PSR_ENABLE;
intel_de_write(dev_priv, intel_de_write(dev_priv,
EDP_PSR_CTL(dev_priv->psr.transcoder), val); EDP_PSR_CTL(dev_priv->psr.transcoder), val);
@ -1012,7 +1014,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
if (!old_crtc_state->has_psr) if (!old_crtc_state->has_psr)
return; return;
if (WARN_ON(!CAN_PSR(dev_priv))) if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
return; return;
mutex_lock(&dev_priv->psr.lock); mutex_lock(&dev_priv->psr.lock);