From 17a839135f7356d9e1cff653ea861b1b890c9d6c Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 17 May 2019 13:39:36 +0800 Subject: [PATCH] drm/amd/powerplay: fix sw SMU wrong UVD/VCE powergate setting The UVD/VCE bits are set wrongly. This causes the UVD/VCE clocks are not brought back correctly on needed. Signed-off-by: Evan Quan Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 940b519686d5..d2eeb6240484 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1834,17 +1834,6 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu, } static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable) -{ - if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT)) - return 0; - - if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT)) - return 0; - - return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable); -} - -static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable) { if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT)) return 0; @@ -1855,6 +1844,17 @@ static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable) return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable); } +static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable) +{ + if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT)) + return 0; + + if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT)) + return 0; + + return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable); +} + static int smu_v11_0_get_current_rpm(struct smu_context *smu, uint32_t *current_rpm) {