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driver: rtc: Add StarFive JH7110 rtc driver
Add RTC driver and support for StarFive JH7110 SoC. Signed-off-by: ziv.xu <ziv.xu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
This commit is contained in:
ziv.xu
Hal Feng
parent
ad6c5a4872
commit
1a3fc138b6
3 changed files with 752 additions and 0 deletions
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@ -1327,6 +1327,14 @@ config RTC_DRV_NTXEC
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embedded controller found in certain e-book readers designed by the
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original design manufacturer Netronix.
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config RTC_DRV_STARFIVE
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tristate "StarFive 32.768k-RTC"
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depends on ARCH_STARFIVE
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depends on OF
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help
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If you say Y here you will get support for the RTC found on
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StarFive SOCS.
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comment "on-CPU RTC drivers"
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config RTC_DRV_ASM9260
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@ -163,6 +163,7 @@ obj-$(CONFIG_RTC_DRV_SH) += rtc-sh.o
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obj-$(CONFIG_RTC_DRV_SNVS) += rtc-snvs.o
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obj-$(CONFIG_RTC_DRV_SPEAR) += rtc-spear.o
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obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
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obj-$(CONFIG_RTC_DRV_STARFIVE) += rtc-starfive.o
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obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
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obj-$(CONFIG_RTC_DRV_ST_LPC) += rtc-st-lpc.o
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obj-$(CONFIG_RTC_DRV_STM32) += rtc-stm32.o
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743
drivers/rtc/rtc-starfive.c
Normal file
743
drivers/rtc/rtc-starfive.c
Normal file
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@ -0,0 +1,743 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RTC driver for the StarFive JH7110 SoC
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*
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* Copyright (C) 2021 StarFive Technology Co., Ltd.
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*/
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#include <asm/delay.h>
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#include <linux/bcd.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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/* Registers */
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#define SFT_RTC_CFG 0x00
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#define SFT_RTC_SW_CAL_VALUE 0x04
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#define SFT_RTC_HW_CAL_CFG 0x08
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#define SFT_RTC_CMP_CFG 0x0C
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#define SFT_RTC_IRQ_EN 0x10
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#define SFT_RTC_IRQ_EVEVT 0x14
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#define SFT_RTC_IRQ_STATUS 0x18
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#define SFT_RTC_CAL_VALUE 0x24
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#define SFT_RTC_CFG_TIME 0x28
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#define SFT_RTC_CFG_DATE 0x2C
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#define SFT_RTC_ACT_TIME 0x34
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#define SFT_RTC_ACT_DATE 0x38
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#define SFT_RTC_TIME 0x3C
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#define SFT_RTC_DATE 0x40
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#define SFT_RTC_TIME_LATCH 0x44
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#define SFT_RTC_DATE_LATCH 0x48
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/* RTC_CFG */
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#define RTC_CFG_ENABLE_SHIFT 0 /* RW: RTC Enable. */
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#define RTC_CFG_CAL_EN_HW_SHIFT 1 /* RW: Enable of hardware calibretion. */
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#define RTC_CFG_CAL_SEL_SHIFT 2 /* RW: select the hw/sw calibretion mode.*/
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#define RTC_CFG_HOUR_MODE_SHIFT 3 /* RW: time hour mode. 24h|12h */
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/* RTC_SW_CAL_VALUE */
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#define RTC_SW_CAL_VALUE_MASK GENMASK(15, 0)
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#define RTC_SW_CAL_MAX RTC_SW_CAL_VALUE_MASK
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#define RTC_SW_CAL_MIN 0
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#define RTC_TICKS_PER_SEC 32768 /* Number of ticks per second */
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#define RTC_PPB_MULT 1000000000LL /* Multiplier for ppb conversions */
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/* RTC_HW_CAL_CFG */
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#define RTC_HW_CAL_REF_SEL_SHIFT 0
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#define RTC_HW_CAL_FRQ_SEL_SHIFT 1
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/* IRQ_EN/IRQ_EVEVT/IRQ_STATUS */
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#define RTC_IRQ_CAL_START BIT(0)
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#define RTC_IRQ_CAL_FINISH BIT(1)
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#define RTC_IRQ_CMP BIT(2)
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#define RTC_IRQ_1SEC BIT(3)
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#define RTC_IRQ_ALAEM BIT(4)
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#define RTC_IRQ_EVT_UPDATE_PSE BIT(31) /* WO: Enable of update time&&date, IRQ_EVEVT only */
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#define RTC_IRQ_ALL (RTC_IRQ_CAL_START \
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| RTC_IRQ_CAL_FINISH \
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| RTC_IRQ_CMP \
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| RTC_IRQ_1SEC \
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| RTC_IRQ_ALAEM)
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/* CAL_VALUE */
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#define RTC_CAL_VALUE_MASK GENMASK(15, 0)
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/* CFG_TIME/ACT_TIME/RTC_TIME */
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#define TIME_SEC_MASK GENMASK(6, 0)
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#define TIME_MIN_MASK GENMASK(13, 7)
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#define TIME_HOUR_MASK GENMASK(20, 14)
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/* CFG_DATE/ACT_DATE/RTC_DATE */
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#define DATE_DAY_MASK GENMASK(5, 0)
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#define DATE_MON_MASK GENMASK(10, 6)
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#define DATE_YEAR_MASK GENMASK(18, 11)
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#define INT_TIMEOUT_US 180
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enum RTC_HOUR_MODE {
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RTC_HOUR_MODE_12H = 0,
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RTC_HOUR_MODE_24H = 1
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};
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enum RTC_CAL_MODE {
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RTC_CAL_MODE_SW = 0,
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RTC_CAL_MODE_HW = 1
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};
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enum RTC_HW_CAL_REF_MODE {
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RTC_CAL_CLK_REF = 0,
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RTC_CAL_CLK_MARK = 1
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};
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static const unsigned long refclk_list[] = {
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1000000,
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2000000,
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4000000,
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5927000,
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6000000,
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7200000,
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8000000,
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10250000,
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11059200,
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12000000,
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12288000,
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13560000,
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16000000,
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19200000,
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20000000,
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22118000,
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24000000,
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24567000,
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25000000,
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26000000,
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27000000,
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30000000,
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32000000,
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33868800,
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36000000,
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36860000,
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40000000,
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44000000,
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50000000,
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54000000,
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28224000,
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28000000,
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};
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struct sft_rtc {
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struct rtc_device *rtc_dev;
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struct completion cal_done;
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struct completion onesec_done;
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struct clk *pclk;
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struct clk *cal_clk;
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struct reset_control *rst_array;
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int hw_cal_map;
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void __iomem *regs;
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int rtc_irq;
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int ms_pulse_irq;
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int one_sec_pulse_irq;
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};
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static inline void sft_rtc_set_enabled(struct sft_rtc *srtc, bool enabled)
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{
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u32 val;
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if (enabled) {
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val = readl(srtc->regs + SFT_RTC_CFG);
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val |= BIT(RTC_CFG_ENABLE_SHIFT);
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writel(val, srtc->regs + SFT_RTC_CFG);
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} else {
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val = readl(srtc->regs + SFT_RTC_CFG);
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val &= ~BIT(RTC_CFG_ENABLE_SHIFT);
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writel(val, srtc->regs + SFT_RTC_CFG);
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}
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}
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static inline bool sft_rtc_get_enabled(struct sft_rtc *srtc)
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{
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return !!(readl(srtc->regs + SFT_RTC_CFG) & BIT(RTC_CFG_ENABLE_SHIFT));
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}
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static inline void sft_rtc_set_mode(struct sft_rtc *srtc, enum RTC_HOUR_MODE mode)
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{
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u32 val;
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val = readl(srtc->regs + SFT_RTC_CFG);
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val |= mode << RTC_CFG_HOUR_MODE_SHIFT;
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writel(val, srtc->regs + SFT_RTC_CFG);
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}
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static inline int sft_rtc_irq_enable(struct sft_rtc *srtc, u32 irq, bool enable)
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{
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u32 val;
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if (!(irq & RTC_IRQ_ALL))
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return -EINVAL;
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if (enable) {
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val = readl(srtc->regs + SFT_RTC_IRQ_EN);
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val |= irq;
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writel(val, srtc->regs + SFT_RTC_IRQ_EN);
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} else {
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val = readl(srtc->regs + SFT_RTC_IRQ_EN);
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val &= ~irq;
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writel(val, srtc->regs + SFT_RTC_IRQ_EN);
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}
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return 0;
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}
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static inline void
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sft_rtc_set_cal_hw_enable(struct sft_rtc *srtc, bool enable)
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{
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u32 val;
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if (enable) {
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val = readl(srtc->regs + SFT_RTC_CFG);
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val |= BIT(RTC_CFG_CAL_EN_HW_SHIFT);
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writel(val, srtc->regs + SFT_RTC_CFG);
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} else {
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val = readl(srtc->regs + SFT_RTC_CFG);
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val &= ~BIT(RTC_CFG_CAL_EN_HW_SHIFT);
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writel(val, srtc->regs + SFT_RTC_CFG);
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}
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}
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static inline void
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sft_rtc_set_cal_mode(struct sft_rtc *srtc, enum RTC_CAL_MODE mode)
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{
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u32 val;
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val = readl(srtc->regs + SFT_RTC_CFG);
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val |= mode << RTC_CFG_CAL_SEL_SHIFT;
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writel(val, srtc->regs + SFT_RTC_CFG);
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}
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static int sft_rtc_get_hw_calclk(struct device *dev, unsigned long freq)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(refclk_list); i++)
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if (refclk_list[i] == freq)
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return i;
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dev_err(dev, "refclk: %ldHz do not support.\n", freq);
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return -EINVAL;
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}
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static inline void sft_rtc_reg2time(struct rtc_time *tm, u32 reg)
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{
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tm->tm_hour = bcd2bin(FIELD_GET(TIME_HOUR_MASK, reg));
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tm->tm_min = bcd2bin(FIELD_GET(TIME_MIN_MASK, reg));
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tm->tm_sec = bcd2bin(FIELD_GET(TIME_SEC_MASK, reg));
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}
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static inline void sft_rtc_reg2date(struct rtc_time *tm, u32 reg)
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{
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tm->tm_year = bcd2bin(FIELD_GET(DATE_YEAR_MASK, reg)) + 100;
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tm->tm_mon = bcd2bin(FIELD_GET(DATE_MON_MASK, reg)) - 1;
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tm->tm_mday = bcd2bin(FIELD_GET(DATE_DAY_MASK, reg));
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}
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static inline u32 sft_rtc_time2reg(struct rtc_time *tm)
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{
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return FIELD_PREP(TIME_HOUR_MASK, bin2bcd(tm->tm_hour)) |
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FIELD_PREP(TIME_MIN_MASK, bin2bcd(tm->tm_min)) |
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FIELD_PREP(TIME_SEC_MASK, bin2bcd(tm->tm_sec));
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}
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static inline u32 sft_rtc_date2reg(struct rtc_time *tm)
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{
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return FIELD_PREP(DATE_YEAR_MASK, bin2bcd(tm->tm_year - 100)) |
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FIELD_PREP(DATE_MON_MASK, bin2bcd(tm->tm_mon + 1)) |
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FIELD_PREP(DATE_DAY_MASK, bin2bcd(tm->tm_mday));
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}
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static inline void sft_rtc_update_pulse(struct sft_rtc *srtc)
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{
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u32 val;
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val = readl(srtc->regs + SFT_RTC_IRQ_EVEVT);
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val |= RTC_IRQ_EVT_UPDATE_PSE;
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writel(val, srtc->regs + SFT_RTC_IRQ_EVEVT);
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}
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static irqreturn_t sft_rtc_irq_handler(int irq, void *data)
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{
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struct sft_rtc *srtc = data;
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struct timerqueue_node *next;
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u32 irq_flags = 0;
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u32 irq_mask = 0;
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u32 val;
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int ret = 0;
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val = readl(srtc->regs + SFT_RTC_IRQ_EVEVT);
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if (val & RTC_IRQ_CAL_START)
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irq_mask |= RTC_IRQ_CAL_START;
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if (val & RTC_IRQ_CAL_FINISH) {
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irq_mask |= RTC_IRQ_CAL_FINISH;
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complete(&srtc->cal_done);
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}
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if (val & RTC_IRQ_CMP)
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irq_mask |= RTC_IRQ_CMP;
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if (val & RTC_IRQ_1SEC) {
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irq_flags |= RTC_PF;
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irq_mask |= RTC_IRQ_1SEC;
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complete(&srtc->onesec_done);
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}
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if (val & RTC_IRQ_ALAEM) {
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irq_flags |= RTC_AF;
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irq_mask |= RTC_IRQ_ALAEM;
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next = timerqueue_getnext(&srtc->rtc_dev->timerqueue);
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if (next == &srtc->rtc_dev->aie_timer.node)
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dev_info(&srtc->rtc_dev->dev, "alarm expires");
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}
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writel(irq_mask, srtc->regs + SFT_RTC_IRQ_EVEVT);
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/* Wait interrupt flag clear */
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ret = readl_poll_timeout_atomic(srtc->regs + SFT_RTC_IRQ_EVEVT, val,
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(val & irq_mask) == 0, 0, INT_TIMEOUT_US);
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if (ret)
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dev_warn(&srtc->rtc_dev->dev, "fail to clear rtc interrupt flag\n");
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if (irq_flags)
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rtc_update_irq(srtc->rtc_dev, 1, irq_flags | RTC_IRQF);
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return IRQ_HANDLED;
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}
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static int sft_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct sft_rtc *srtc = dev_get_drvdata(dev);
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u32 val;
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int irq_1sec_state_start, irq_1sec_state_end;
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/* If the RTC is disabled, assume the values are invalid */
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if (!sft_rtc_get_enabled(srtc))
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return -EINVAL;
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irq_1sec_state_start =
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(readl(srtc->regs + SFT_RTC_IRQ_STATUS) & RTC_IRQ_1SEC) == 0 ? 0 : 1;
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read_again:
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val = readl(srtc->regs + SFT_RTC_TIME);
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sft_rtc_reg2time(tm, val);
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val = readl(srtc->regs + SFT_RTC_DATE);
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sft_rtc_reg2date(tm, val);
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if (irq_1sec_state_start == 0) {
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irq_1sec_state_end =
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(readl(srtc->regs + SFT_RTC_IRQ_STATUS) & RTC_IRQ_1SEC) == 0 ? 0 : 1;
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if (irq_1sec_state_end == 1) {
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irq_1sec_state_start = 1;
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goto read_again;
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}
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}
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return 0;
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}
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static int sft_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct sft_rtc *srtc = dev_get_drvdata(dev);
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u32 val;
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int ret;
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val = sft_rtc_time2reg(tm);
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writel(val, srtc->regs + SFT_RTC_CFG_TIME);
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val = sft_rtc_date2reg(tm);
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writel(val, srtc->regs + SFT_RTC_CFG_DATE);
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/* Update pulse */
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sft_rtc_update_pulse(srtc);
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/* Ensure that data is fully written */
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ret = wait_for_completion_interruptible_timeout(&srtc->onesec_done,
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usecs_to_jiffies(120));
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if (ret) {
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dev_warn(dev,
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"rtc wait for completion interruptible timeout.\n");
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}
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return 0;
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}
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static int sft_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct sft_rtc *srtc = dev_get_drvdata(dev);
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return sft_rtc_irq_enable(srtc, RTC_IRQ_ALAEM, enabled);
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}
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static int sft_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct sft_rtc *srtc = dev_get_drvdata(dev);
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u32 val;
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val = readl(srtc->regs + SFT_RTC_ACT_TIME);
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sft_rtc_reg2time(&alarm->time, val);
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val = readl(srtc->regs + SFT_RTC_ACT_DATE);
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sft_rtc_reg2date(&alarm->time, val);
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return 0;
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}
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static int sft_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct sft_rtc *srtc = dev_get_drvdata(dev);
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u32 val;
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sft_rtc_alarm_irq_enable(dev, 0);
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val = sft_rtc_time2reg(&alarm->time);
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writel(val, srtc->regs + SFT_RTC_ACT_TIME);
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val = sft_rtc_date2reg(&alarm->time);
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writel(val, srtc->regs + SFT_RTC_ACT_DATE);
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sft_rtc_alarm_irq_enable(dev, alarm->enabled);
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return 0;
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}
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static int sft_rtc_get_offset(struct device *dev, long *offset)
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{
|
||||
struct sft_rtc *srtc = dev_get_drvdata(dev);
|
||||
s64 tmp;
|
||||
u32 val;
|
||||
|
||||
val = readl(srtc->regs + SFT_RTC_CAL_VALUE)
|
||||
& RTC_SW_CAL_VALUE_MASK;
|
||||
val += 1;
|
||||
/*
|
||||
* the adjust val range is [0x0000-0xffff],
|
||||
* the default val is 0x7fff (32768-1),mapping offset=0 ;
|
||||
*/
|
||||
tmp = (s64)val - RTC_TICKS_PER_SEC;
|
||||
tmp *= RTC_PPB_MULT;
|
||||
tmp = div_s64(tmp, RTC_TICKS_PER_SEC);
|
||||
|
||||
/* Offset value operates in negative way, so swap sign */
|
||||
*offset = -tmp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sft_rtc_set_offset(struct device *dev, long offset)
|
||||
{
|
||||
struct sft_rtc *srtc = dev_get_drvdata(dev);
|
||||
s64 tmp;
|
||||
u32 val;
|
||||
|
||||
tmp = offset * RTC_TICKS_PER_SEC;
|
||||
tmp = div_s64(tmp, RTC_PPB_MULT);
|
||||
|
||||
tmp = RTC_TICKS_PER_SEC - tmp;
|
||||
tmp -= 1;
|
||||
if (tmp > RTC_SW_CAL_MAX || tmp < RTC_SW_CAL_MIN) {
|
||||
dev_err(dev, "offset is out of range.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = tmp & RTC_SW_CAL_VALUE_MASK;
|
||||
/* set software calibration value */
|
||||
writel(val, srtc->regs + SFT_RTC_SW_CAL_VALUE);
|
||||
|
||||
/* set CFG_RTC-cal_sel to select calibretion by software. */
|
||||
sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_SW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int
|
||||
sft_rtc_hw_adjustment(struct device *dev, unsigned int enable)
|
||||
{
|
||||
struct sft_rtc *srtc = dev_get_drvdata(dev);
|
||||
u32 val;
|
||||
|
||||
if (srtc->hw_cal_map <= 0) {
|
||||
dev_err(dev, "fail to get cal-clock-freq.\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
sft_rtc_irq_enable(srtc, RTC_IRQ_CAL_FINISH, true);
|
||||
|
||||
/* Set reference clock frequency value */
|
||||
val = readl(srtc->regs + SFT_RTC_HW_CAL_CFG);
|
||||
val |= (srtc->hw_cal_map << RTC_HW_CAL_FRQ_SEL_SHIFT);
|
||||
writel(val, srtc->regs + SFT_RTC_HW_CAL_CFG);
|
||||
|
||||
/* Set CFG_RTC-cal_sel to select calibretion by hardware. */
|
||||
sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_HW);
|
||||
|
||||
/* Set CFG_RTC-cal_en_hw to launch hardware calibretion.*/
|
||||
sft_rtc_set_cal_hw_enable(srtc, true);
|
||||
|
||||
wait_for_completion_interruptible_timeout(&srtc->cal_done,
|
||||
usecs_to_jiffies(100));
|
||||
|
||||
sft_rtc_irq_enable(srtc, RTC_IRQ_CAL_FINISH, false);
|
||||
} else {
|
||||
sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_SW);
|
||||
sft_rtc_set_cal_hw_enable(srtc, false);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sft_rtc_get_cal_clk(struct device *dev, struct sft_rtc *srtc)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
unsigned long cal_clk_freq;
|
||||
u32 freq;
|
||||
int ret;
|
||||
|
||||
srtc->cal_clk = devm_clk_get(dev, "cal_clk");
|
||||
if (IS_ERR(srtc->cal_clk))
|
||||
return PTR_ERR(srtc->cal_clk);
|
||||
|
||||
clk_prepare_enable(srtc->cal_clk);
|
||||
|
||||
cal_clk_freq = clk_get_rate(srtc->cal_clk);
|
||||
if (!cal_clk_freq) {
|
||||
dev_warn(dev,
|
||||
"get rate failed, next try to get from dts.\n");
|
||||
ret = of_property_read_u32(np, "rtc,cal-clock-freq", &freq);
|
||||
if (!ret) {
|
||||
cal_clk_freq = (u64)freq;
|
||||
} else {
|
||||
dev_err(dev,
|
||||
"Need rtc,cal-clock-freq define in dts.\n");
|
||||
goto err_disable_cal_clk;
|
||||
}
|
||||
}
|
||||
|
||||
srtc->hw_cal_map = sft_rtc_get_hw_calclk(dev, cal_clk_freq);
|
||||
if (srtc->hw_cal_map < 0) {
|
||||
ret = srtc->hw_cal_map;
|
||||
goto err_disable_cal_clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_cal_clk:
|
||||
clk_disable_unprepare(srtc->cal_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sft_rtc_get_irq(struct platform_device *pdev, struct sft_rtc *srtc)
|
||||
{
|
||||
int ret;
|
||||
|
||||
srtc->rtc_irq = platform_get_irq_byname(pdev, "rtc");
|
||||
if (srtc->rtc_irq < 0)
|
||||
return -EINVAL;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, srtc->rtc_irq,
|
||||
sft_rtc_irq_handler, 0,
|
||||
KBUILD_MODNAME, srtc);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Failed to request interrupt, %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rtc_class_ops starfive_rtc_ops = {
|
||||
.read_time = sft_rtc_read_time,
|
||||
.set_time = sft_rtc_set_time,
|
||||
.read_alarm = sft_rtc_read_alarm,
|
||||
.set_alarm = sft_rtc_set_alarm,
|
||||
.alarm_irq_enable = sft_rtc_alarm_irq_enable,
|
||||
.set_offset = sft_rtc_set_offset,
|
||||
.read_offset = sft_rtc_get_offset,
|
||||
};
|
||||
|
||||
static int sft_rtc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sft_rtc *srtc;
|
||||
struct rtc_time tm;
|
||||
struct irq_desc *desc;
|
||||
int ret;
|
||||
|
||||
srtc = devm_kzalloc(dev, sizeof(*srtc), GFP_KERNEL);
|
||||
if (!srtc)
|
||||
return -ENOMEM;
|
||||
|
||||
srtc->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(srtc->regs))
|
||||
return PTR_ERR(srtc->regs);
|
||||
|
||||
srtc->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(srtc->pclk)) {
|
||||
ret = PTR_ERR(srtc->pclk);
|
||||
dev_err(dev,
|
||||
"Failed to retrieve the peripheral clock, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
srtc->rst_array = devm_reset_control_array_get_exclusive(dev);
|
||||
if (IS_ERR(srtc->rst_array)) {
|
||||
ret = PTR_ERR(srtc->rst_array);
|
||||
dev_err(dev,
|
||||
"Failed to retrieve the rtc reset, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
init_completion(&srtc->cal_done);
|
||||
init_completion(&srtc->onesec_done);
|
||||
|
||||
ret = clk_prepare_enable(srtc->pclk);
|
||||
if (ret) {
|
||||
dev_err(dev,
|
||||
"Failed to enable the peripheral clock, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = sft_rtc_get_cal_clk(dev, srtc);
|
||||
if (ret)
|
||||
goto err_disable_pclk;
|
||||
|
||||
ret = reset_control_deassert(srtc->rst_array);
|
||||
if (ret) {
|
||||
dev_err(dev,
|
||||
"Failed to deassert rtc resets, %d\n", ret);
|
||||
goto err_disable_cal_clk;
|
||||
}
|
||||
|
||||
ret = sft_rtc_get_irq(pdev, srtc);
|
||||
if (ret)
|
||||
goto err_disable_cal_clk;
|
||||
|
||||
srtc->rtc_dev = devm_rtc_allocate_device(dev);
|
||||
if (IS_ERR(srtc->rtc_dev))
|
||||
return PTR_ERR(srtc->rtc_dev);
|
||||
|
||||
platform_set_drvdata(pdev, srtc);
|
||||
|
||||
/* The RTC supports 01.01.2001 - 31.12.2099 */
|
||||
srtc->rtc_dev->range_min = mktime64(2001, 1, 1, 0, 0, 0);
|
||||
srtc->rtc_dev->range_max = mktime64(2099, 12, 31, 23, 59, 59);
|
||||
|
||||
srtc->rtc_dev->ops = &starfive_rtc_ops;
|
||||
device_init_wakeup(dev, true);
|
||||
|
||||
desc = irq_to_desc(srtc->rtc_irq);
|
||||
irq_desc_get_chip(desc)->flags = IRQCHIP_SKIP_SET_WAKE;
|
||||
|
||||
/* Always use 24-hour mode and keep the RTC values */
|
||||
sft_rtc_set_mode(srtc, RTC_HOUR_MODE_24H);
|
||||
|
||||
sft_rtc_set_enabled(srtc, true);
|
||||
|
||||
if (device_property_read_bool(dev, "rtc,hw-adjustment"))
|
||||
sft_rtc_hw_adjustment(dev, true);
|
||||
|
||||
/*
|
||||
* If rtc time is out of supported range, reset it to the minimum time.
|
||||
* notice that, actual year = 1900 + tm.tm_year
|
||||
* actual month = 1 + tm.tm_mon
|
||||
*/
|
||||
sft_rtc_read_time(dev, &tm);
|
||||
if (tm.tm_year < 101 || tm.tm_year > 199 || tm.tm_mon < 0 || tm.tm_mon > 11 ||
|
||||
tm.tm_mday < 1 || tm.tm_mday > 31 || tm.tm_hour < 0 || tm.tm_hour > 23 ||
|
||||
tm.tm_min < 0 || tm.tm_min > 59 || tm.tm_sec < 0 || tm.tm_sec > 59) {
|
||||
rtc_time64_to_tm(srtc->rtc_dev->range_min, &tm);
|
||||
sft_rtc_set_time(dev, &tm);
|
||||
}
|
||||
|
||||
ret = devm_rtc_register_device(srtc->rtc_dev);
|
||||
if (ret)
|
||||
goto err_disable_wakeup;
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_wakeup:
|
||||
device_init_wakeup(dev, false);
|
||||
|
||||
err_disable_cal_clk:
|
||||
clk_disable_unprepare(srtc->cal_clk);
|
||||
|
||||
err_disable_pclk:
|
||||
clk_disable_unprepare(srtc->pclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sft_rtc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sft_rtc *srtc = platform_get_drvdata(pdev);
|
||||
|
||||
sft_rtc_alarm_irq_enable(&pdev->dev, 0);
|
||||
device_init_wakeup(&pdev->dev, 0);
|
||||
|
||||
clk_disable_unprepare(srtc->pclk);
|
||||
clk_disable_unprepare(srtc->cal_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int sft_rtc_suspend(struct device *dev)
|
||||
{
|
||||
struct sft_rtc *srtc = dev_get_drvdata(dev);
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
enable_irq_wake(srtc->rtc_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sft_rtc_resume(struct device *dev)
|
||||
{
|
||||
struct sft_rtc *srtc = dev_get_drvdata(dev);
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
disable_irq_wake(srtc->rtc_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(sft_rtc_pm_ops, sft_rtc_suspend, sft_rtc_resume);
|
||||
|
||||
static const struct of_device_id sft_rtc_of_match[] = {
|
||||
{ .compatible = "starfive,jh7110-rtc" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sft_rtc_of_match);
|
||||
|
||||
static struct platform_driver starfive_rtc_driver = {
|
||||
.driver = {
|
||||
.name = "starfive-rtc",
|
||||
.of_match_table = sft_rtc_of_match,
|
||||
.pm = &sft_rtc_pm_ops,
|
||||
},
|
||||
.probe = sft_rtc_probe,
|
||||
.remove = sft_rtc_remove,
|
||||
};
|
||||
module_platform_driver(starfive_rtc_driver);
|
||||
|
||||
MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
|
||||
MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
|
||||
MODULE_DESCRIPTION("StarFive RTC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:starfive-rtc");
|
||||
Loading…
Add table
Reference in a new issue