mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-06-21 14:11:20 +00:00
ARM: Device-tree updates
New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants
of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST
+ Reference boards for stm32mp15
- ST Ericsson
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
variants of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner:
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic:
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip:
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST:
+ Reference boards for stm32mp15
- ST Ericsson:
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP:
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm:
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
arm64: dts: ti: k3-am65-main Add CAL node
arm64: dts: ti: k3-j721e-main: Add McASP nodes
arm64: dts: ti: k3-am654-main: Add McASP nodes
arm64: dts: ti: k3-j721e: DMA support
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
arm64: dts: ti: k3-am65: DMA support
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
ARM: dts: aspeed: rainier: Switch PSUs to unknown version
arm64: dts: rockchip: Kill off "simple-panel" compatibles
ARM: dts: rockchip: Kill off "simple-panel" compatibles
arm64: dts: rockchip: rename dwmmc node names to mmc
ARM: dts: rockchip: rename dwmmc node names to mmc
arm64: dts: exynos: Rename Samsung and Exynos to lowercase
arm64: dts: uniphier: add reset-names to NAND controller node
...
This commit is contained in:
Linus Torvalds
commit
1afa9c3b7c
585 changed files with 32247 additions and 15797 deletions
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@ -72,6 +72,8 @@
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#define MMP2_CLK_CCIC1_PHY 118
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#define MMP2_CLK_CCIC1_SPHY 119
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#define MMP2_CLK_DISP0_LCDC 120
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#define MMP2_CLK_USBHSIC0 121
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#define MMP2_CLK_USBHSIC1 122
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#define MMP2_NR_CLKS 200
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#endif
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@ -108,4 +108,143 @@
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#define TEGRA186_SID_SE_VM6 0x4e
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#define TEGRA186_SID_SE_VM7 0x4f
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/*
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* memory client IDs
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*/
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/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
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#define TEGRA186_MEMORY_CLIENT_PTCR 0x00
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/* PCIE reads */
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#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e
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/* High-definition audio (HDA) reads */
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#define TEGRA186_MEMORY_CLIENT_HDAR 0x15
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/* Host channel data reads */
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#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16
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#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c
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/* SATA reads */
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#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f
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/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27
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#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b
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/* PCIE writes */
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#define TEGRA186_MEMORY_CLIENT_AFIW 0x31
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/* High-definition audio (HDA) writes */
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#define TEGRA186_MEMORY_CLIENT_HDAW 0x35
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/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39
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/* SATA writes */
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#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d
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/* ISP Read client for Crossbar A */
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#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44
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/* ISP Write client for Crossbar A */
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#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46
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/* ISP Write client Crossbar B */
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#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47
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/* XUSB reads */
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#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a
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/* XUSB_HOST writes */
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#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b
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/* XUSB reads */
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#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c
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/* XUSB_DEV writes */
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#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d
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/* TSEC Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54
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/* TSEC Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55
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/* 3D, ltcx reads instance 0 */
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#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58
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/* 3D, ltcx writes instance 0 */
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#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59
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/* sdmmca memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60
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/* sdmmcbmemory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61
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/* sdmmc memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62
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/* sdmmcd memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmca memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64
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/* sdmmcb memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65
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/* sdmmc memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66
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/* sdmmcd memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67
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#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c
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#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d
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/* VI Write client */
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#define TEGRA186_MEMORY_CLIENT_VIW 0x72
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#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78
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#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79
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/* Audio Processing (APE) engine reads */
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#define TEGRA186_MEMORY_CLIENT_APER 0x7a
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/* Audio Processing (APE) engine writes */
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#define TEGRA186_MEMORY_CLIENT_APEW 0x7b
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#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e
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#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f
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/* SE Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_SESRD 0x80
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/* SE Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_SESWR 0x81
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/* ETR reads */
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#define TEGRA186_MEMORY_CLIENT_ETRR 0x84
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/* ETR writes */
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#define TEGRA186_MEMORY_CLIENT_ETRW 0x85
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/* TSECB Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86
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/* TSECB Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87
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/* 3D, ltcx reads instance 1 */
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#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88
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/* 3D, ltcx writes instance 1 */
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#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89
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/* AXI Switch read client */
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#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c
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/* AXI Switch write client */
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#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d
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/* EQOS read client */
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#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e
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/* EQOS write client */
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#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f
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/* UFSHC read client */
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#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90
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/* UFSHC write client */
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#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91
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/* NVDISPLAY read client */
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#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92
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/* BPMP read client */
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#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94
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/* BPMPDMA read client */
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#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96
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/* AON read client */
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#define TEGRA186_MEMORY_CLIENT_AONR 0x97
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/* AON write client */
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#define TEGRA186_MEMORY_CLIENT_AONW 0x98
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/* AONDMA read client */
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#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99
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/* AONDMA write client */
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#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a
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/* SCE read client */
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#define TEGRA186_MEMORY_CLIENT_SCER 0x9b
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/* SCE write client */
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#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c
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/* SCEDMA read client */
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#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d
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/* SCEDMA write client */
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#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e
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/* APEDMA read client */
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#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f
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/* APEDMA write client */
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#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0
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/* NVDISPLAY read client instance 2 */
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#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1
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#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2
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#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3
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#endif
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410
include/dt-bindings/memory/tegra194-mc.h
Normal file
410
include/dt-bindings/memory/tegra194-mc.h
Normal file
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@ -0,0 +1,410 @@
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#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA194_MC_H
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/* special clients */
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#define TEGRA194_SID_INVALID 0x00
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#define TEGRA194_SID_PASSTHROUGH 0x7f
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/* host1x clients */
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#define TEGRA194_SID_HOST1X 0x01
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#define TEGRA194_SID_CSI 0x02
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#define TEGRA194_SID_VIC 0x03
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#define TEGRA194_SID_VI 0x04
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#define TEGRA194_SID_ISP 0x05
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#define TEGRA194_SID_NVDEC 0x06
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#define TEGRA194_SID_NVENC 0x07
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#define TEGRA194_SID_NVJPG 0x08
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#define TEGRA194_SID_NVDISPLAY 0x09
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#define TEGRA194_SID_TSEC 0x0a
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#define TEGRA194_SID_TSECB 0x0b
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#define TEGRA194_SID_SE 0x0c
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#define TEGRA194_SID_SE1 0x0d
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#define TEGRA194_SID_SE2 0x0e
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#define TEGRA194_SID_SE3 0x0f
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/* GPU clients */
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#define TEGRA194_SID_GPU 0x10
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/* other SoC clients */
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#define TEGRA194_SID_AFI 0x11
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#define TEGRA194_SID_HDA 0x12
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#define TEGRA194_SID_ETR 0x13
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#define TEGRA194_SID_EQOS 0x14
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#define TEGRA194_SID_UFSHC 0x15
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#define TEGRA194_SID_AON 0x16
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#define TEGRA194_SID_SDMMC4 0x17
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#define TEGRA194_SID_SDMMC3 0x18
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#define TEGRA194_SID_SDMMC2 0x19
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#define TEGRA194_SID_SDMMC1 0x1a
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#define TEGRA194_SID_XUSB_HOST 0x1b
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#define TEGRA194_SID_XUSB_DEV 0x1c
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#define TEGRA194_SID_SATA 0x1d
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#define TEGRA194_SID_APE 0x1e
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#define TEGRA194_SID_SCE 0x1f
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/* GPC DMA clients */
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#define TEGRA194_SID_GPCDMA_0 0x20
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#define TEGRA194_SID_GPCDMA_1 0x21
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#define TEGRA194_SID_GPCDMA_2 0x22
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#define TEGRA194_SID_GPCDMA_3 0x23
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#define TEGRA194_SID_GPCDMA_4 0x24
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#define TEGRA194_SID_GPCDMA_5 0x25
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#define TEGRA194_SID_GPCDMA_6 0x26
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#define TEGRA194_SID_GPCDMA_7 0x27
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/* APE DMA clients */
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#define TEGRA194_SID_APE_1 0x28
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#define TEGRA194_SID_APE_2 0x29
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/* camera RTCPU */
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#define TEGRA194_SID_RCE 0x2a
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/* camera RTCPU on host1x address space */
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#define TEGRA194_SID_RCE_1X 0x2b
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/* APE DMA clients */
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#define TEGRA194_SID_APE_3 0x2c
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/* camera RTCPU running on APE */
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#define TEGRA194_SID_APE_CAM 0x2d
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#define TEGRA194_SID_APE_CAM_1X 0x2e
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#define TEGRA194_SID_RCE_RM 0x2f
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#define TEGRA194_SID_VI_FALCON 0x30
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#define TEGRA194_SID_ISP_FALCON 0x31
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/*
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* The BPMP has its SID value hardcoded in the firmware. Changing it requires
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* considerable effort.
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*/
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#define TEGRA194_SID_BPMP 0x32
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/* for SMMU tests */
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#define TEGRA194_SID_SMMU_TEST 0x33
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/* host1x virtualization channels */
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#define TEGRA194_SID_HOST1X_CTX0 0x38
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#define TEGRA194_SID_HOST1X_CTX1 0x39
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#define TEGRA194_SID_HOST1X_CTX2 0x3a
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#define TEGRA194_SID_HOST1X_CTX3 0x3b
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#define TEGRA194_SID_HOST1X_CTX4 0x3c
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#define TEGRA194_SID_HOST1X_CTX5 0x3d
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#define TEGRA194_SID_HOST1X_CTX6 0x3e
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#define TEGRA194_SID_HOST1X_CTX7 0x3f
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/* host1x command buffers */
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#define TEGRA194_SID_HOST1X_VM0 0x40
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#define TEGRA194_SID_HOST1X_VM1 0x41
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#define TEGRA194_SID_HOST1X_VM2 0x42
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#define TEGRA194_SID_HOST1X_VM3 0x43
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#define TEGRA194_SID_HOST1X_VM4 0x44
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#define TEGRA194_SID_HOST1X_VM5 0x45
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#define TEGRA194_SID_HOST1X_VM6 0x46
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#define TEGRA194_SID_HOST1X_VM7 0x47
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/* SE data buffers */
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#define TEGRA194_SID_SE_VM0 0x48
|
||||
#define TEGRA194_SID_SE_VM1 0x49
|
||||
#define TEGRA194_SID_SE_VM2 0x4a
|
||||
#define TEGRA194_SID_SE_VM3 0x4b
|
||||
#define TEGRA194_SID_SE_VM4 0x4c
|
||||
#define TEGRA194_SID_SE_VM5 0x4d
|
||||
#define TEGRA194_SID_SE_VM6 0x4e
|
||||
#define TEGRA194_SID_SE_VM7 0x4f
|
||||
|
||||
#define TEGRA194_SID_MIU 0x50
|
||||
|
||||
#define TEGRA194_SID_NVDLA0 0x51
|
||||
#define TEGRA194_SID_NVDLA1 0x52
|
||||
|
||||
#define TEGRA194_SID_PVA0 0x53
|
||||
#define TEGRA194_SID_PVA1 0x54
|
||||
#define TEGRA194_SID_NVENC1 0x55
|
||||
#define TEGRA194_SID_PCIE0 0x56
|
||||
#define TEGRA194_SID_PCIE1 0x57
|
||||
#define TEGRA194_SID_PCIE2 0x58
|
||||
#define TEGRA194_SID_PCIE3 0x59
|
||||
#define TEGRA194_SID_PCIE4 0x5a
|
||||
#define TEGRA194_SID_PCIE5 0x5b
|
||||
#define TEGRA194_SID_NVDEC1 0x5c
|
||||
|
||||
#define TEGRA194_SID_XUSB_VF0 0x5d
|
||||
#define TEGRA194_SID_XUSB_VF1 0x5e
|
||||
#define TEGRA194_SID_XUSB_VF2 0x5f
|
||||
#define TEGRA194_SID_XUSB_VF3 0x60
|
||||
|
||||
#define TEGRA194_SID_RCE_VM3 0x61
|
||||
#define TEGRA194_SID_VI_VM2 0x62
|
||||
#define TEGRA194_SID_VI_VM3 0x63
|
||||
#define TEGRA194_SID_RCE_SERVER 0x64
|
||||
|
||||
/*
|
||||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
|
||||
#define TEGRA194_MEMORY_CLIENT_PTCR 0x00
|
||||
/* MSS internal memqual MIU7 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01
|
||||
/* MSS internal memqual MIU7 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02
|
||||
/* High-definition audio (HDA) read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HDAR 0x15
|
||||
/* Host channel data read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c
|
||||
/* SATA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f
|
||||
/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b
|
||||
/* High-definition audio (HDA) write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_HDAW 0x35
|
||||
/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
|
||||
#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39
|
||||
/* SATA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d
|
||||
/* ISP read client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44
|
||||
/* ISP read client 1 for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45
|
||||
/* ISP Write client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46
|
||||
/* ISP Write client Crossbar B */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47
|
||||
/* XUSB_HOST read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a
|
||||
/* XUSB_HOST write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b
|
||||
/* XUSB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c
|
||||
/* XUSB_DEV write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d
|
||||
/* sdmmca memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60
|
||||
/* sdmmc memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62
|
||||
/* sdmmcd memory read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63
|
||||
/* sdmmca memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64
|
||||
/* sdmmc memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66
|
||||
/* sdmmcd memory write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d
|
||||
/* VI Write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIW 0x72
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79
|
||||
/* Audio Processing (APE) engine read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_APER 0x7a
|
||||
/* Audio Processing (APE) engine write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEW 0x7b
|
||||
#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e
|
||||
#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f
|
||||
/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82
|
||||
/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83
|
||||
/* ETR read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_ETRR 0x84
|
||||
/* ETR write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_ETRW 0x85
|
||||
/* AXI Switch read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c
|
||||
/* AXI Switch write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d
|
||||
/* EQOS read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e
|
||||
/* EQOS write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f
|
||||
/* UFSHC read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90
|
||||
/* UFSHC write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91
|
||||
/* NVDISPLAY read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92
|
||||
/* BPMP read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94
|
||||
/* BPMPDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95
|
||||
/* BPMPDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96
|
||||
/* AON read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONR 0x97
|
||||
/* AON write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONW 0x98
|
||||
/* AONDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99
|
||||
/* AONDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a
|
||||
/* SCE read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCER 0x9b
|
||||
/* SCE write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c
|
||||
/* SCEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d
|
||||
/* SCEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e
|
||||
/* APEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f
|
||||
/* APEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0
|
||||
/* NVDISPLAY read client instance 2 */
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1
|
||||
#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3
|
||||
/* MSS internal memqual MIU0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6
|
||||
/* MSS internal memqual MIU0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7
|
||||
/* MSS internal memqual MIU1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8
|
||||
/* MSS internal memqual MIU1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9
|
||||
/* MSS internal memqual MIU2 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae
|
||||
/* MSS internal memqual MIU2 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf
|
||||
/* MSS internal memqual MIU3 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0
|
||||
/* MSS internal memqual MIU3 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1
|
||||
/* MSS internal memqual MIU4 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2
|
||||
/* MSS internal memqual MIU4 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3
|
||||
#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4
|
||||
#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb
|
||||
/* VI FLACON read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc
|
||||
/* VIFAL write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd
|
||||
/* DLA0ARDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe
|
||||
/* DLA0 Falcon read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf
|
||||
/* DLA0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0
|
||||
/* DLA0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1
|
||||
/* DLA1ARDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2
|
||||
/* DLA1 Falcon read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3
|
||||
/* DLA1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4
|
||||
/* DLA1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5
|
||||
/* PVA0RDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6
|
||||
/* PVA0RDB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7
|
||||
/* PVA0RDC read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8
|
||||
/* PVA0WRA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9
|
||||
/* PVA0WRB write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca
|
||||
/* PVA0WRC write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb
|
||||
/* PVA1RDA read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc
|
||||
/* PVA1RDB read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd
|
||||
/* PVA1RDC read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce
|
||||
/* PVA1WRA write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf
|
||||
/* PVA1WRB write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0
|
||||
/* PVA1WRC write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1
|
||||
/* RCE read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCER 0xd2
|
||||
/* RCE write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3
|
||||
/* RCEDMA read client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4
|
||||
/* RCEDMA write client */
|
||||
#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7
|
||||
/* PCIE0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8
|
||||
/* PCIE0 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9
|
||||
/* PCIE1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda
|
||||
/* PCIE1 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb
|
||||
/* PCIE2 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc
|
||||
/* PCIE2 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd
|
||||
/* PCIE3 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde
|
||||
/* PCIE3 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf
|
||||
/* PCIE4 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0
|
||||
/* PCIE4 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1
|
||||
/* PCIE5 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2
|
||||
/* PCIE5 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3
|
||||
/* ISP read client 1 for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8
|
||||
/* DLA0ARDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9
|
||||
/* DLA1ARDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea
|
||||
/* PVA0RDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb
|
||||
/* PVA0RDB1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec
|
||||
/* PVA1RDA1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed
|
||||
/* PVA1RDB1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee
|
||||
/* PCIE5r1 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0
|
||||
#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1
|
||||
/* ISP read client for Crossbar A */
|
||||
#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2
|
||||
/* PCIE0 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7
|
||||
#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa
|
||||
#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb
|
||||
/* MSS internal memqual MIU5 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc
|
||||
/* MSS internal memqual MIU5 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd
|
||||
/* MSS internal memqual MIU6 read clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe
|
||||
/* MSS internal memqual MIU6 write clients */
|
||||
#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue