From 8765caa5cb6054247832947119ea533b5d410d2b Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 29 Aug 2016 21:49:56 +0800 Subject: [PATCH 1/4] ARM: imx: rename imx6q_set_int_mem_clk_lpm() function Let's rename the function imx6q_set_int_mem_clk_lpm() to imx6_set_int_mem_clk_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 2 +- arch/arm/mach-imx/cpuidle-imx6q.c | 2 +- arch/arm/mach-imx/pm-imx6.c | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index a8f469333027..fb644304446c 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -109,7 +109,7 @@ void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_int_mem_clk_lpm(bool enable); +void imx6_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); int imx_mmdc_get_ddr_type(void); diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index db0f48c4b17e..bfeb25aaf9a2 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -85,7 +85,7 @@ EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused); int __init imx6q_cpuidle_init(void) { /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ - imx6q_set_int_mem_clk_lpm(true); + imx6_set_int_mem_clk_lpm(true); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 58924b3844df..549648309deb 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -217,7 +217,7 @@ struct imx6_cpu_pm_info { u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ } __aligned(8); -void imx6q_set_int_mem_clk_lpm(bool enable) +void imx6_set_int_mem_clk_lpm(bool enable) { u32 val = readl_relaxed(ccm_base + CGPR); @@ -367,7 +367,7 @@ static int imx6q_pm_enter(suspend_state_t state) switch (state) { case PM_SUSPEND_STANDBY: imx6_set_lpm(STOP_POWER_ON); - imx6q_set_int_mem_clk_lpm(true); + imx6_set_int_mem_clk_lpm(true); imx_gpc_pre_suspend(false); if (cpu_is_imx6sl()) imx6sl_set_wait_clk(true); @@ -380,7 +380,7 @@ static int imx6q_pm_enter(suspend_state_t state) break; case PM_SUSPEND_MEM: imx6_set_lpm(STOP_POWER_OFF); - imx6q_set_int_mem_clk_lpm(false); + imx6_set_int_mem_clk_lpm(false); imx6q_enable_wb(true); /* * For suspend into ocram, asm code already take care of @@ -398,7 +398,7 @@ static int imx6q_pm_enter(suspend_state_t state) imx_gpc_post_resume(); imx6_enable_rbc(false); imx6q_enable_wb(false); - imx6q_set_int_mem_clk_lpm(true); + imx6_set_int_mem_clk_lpm(true); imx6_set_lpm(WAIT_CLOCKED); break; default: From 6ae44aa651d0d82097cb5379be94e86beade9c7b Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 29 Aug 2016 21:49:57 +0800 Subject: [PATCH 2/4] ARM: imx: enable WAIT mode hardware workaround for imx6sx Need to enable INT_MEM_CLK_LPM bit in CCM_CGPR for WAIT mode, without this bit set, if there is pending interrupt during ARM platform entering WAIT mode without power gating, cache data will be corrupted, this is a hardware workaround for WAIT mode and must be enabled. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpuidle-imx6sx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 3c6672b3796b..261aaa45ff33 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -90,6 +90,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = { int __init imx6sx_cpuidle_init(void) { + imx6_set_int_mem_clk_lpm(true); imx6_enable_rbc(false); /* * set ARM power up/down timing to the fastest, From 547e8f526959ded88b93dbdbbb6c8549138fefa8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 29 Aug 2016 23:41:12 +0800 Subject: [PATCH 3/4] ARM: imx: add cpuidle support for i.mx6ul This patch enables cpuidle driver for i.MX6UL, it reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle supported: 1. ARM WFI; 2. SOC in WAIT mode; 3. SOC in WAIT mode + ARM power off. As i.MX6UL has cortex-A7 CORE with an internal L2 cache, so flushing it before powering down ARM platform is necessary, flush_cache_all() in last step of cpu_suspend has very small overhead, just call it to avoid cache type check for different platforms. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpuidle-imx6sx.c | 10 ++++++++++ arch/arm/mach-imx/mach-imx6ul.c | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 261aaa45ff33..c5a5c3a70ab1 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,15 @@ static int imx6sx_idle_finish(unsigned long val) { + /* + * for Cortex-A7 which has an internal L2 + * cache, need to flush it before powering + * down ARM platform, since flushing L1 cache + * here again has very small overhead, compared + * to adding conditional code for L2 cache type, + * just call flush_cache_all() is fine. + */ + flush_cache_all(); cpu_do_idle(); return 0; diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 5d9bfab279dd..08308a127ff7 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -16,6 +16,7 @@ #include #include "common.h" +#include "cpuidle.h" static void __init imx6ul_enet_clk_init(void) { @@ -79,6 +80,8 @@ static void __init imx6ul_init_irq(void) static void __init imx6ul_init_late(void) { + imx6sx_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); } From d64299daf44c7ff57120a379ceb4907f19bbf041 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 6 Sep 2016 14:53:25 +0200 Subject: [PATCH 4/4] ARM: imx: build cpuidle-imx6sx.o for imx6ul The imx6ul soc code gained support for cpuidle, but that causes a link failure if CONFIG_SOC_IMX6SX is disabled: arch/arm/mach-imx/mach-imx6ul.o: In function `imx6ul_init_late': mach-imx6ul.c:(.init.text+0xc): undefined reference to `imx6sx_cpuidle_init' This adds the file containing the imx6sx_cpuidle_init function to the kernel for 6ul-only configurations. Signed-off-by: Arnd Bergmann Fixes: 547e8f526959 ("ARM: imx: add cpuidle support for i.mx6ul") Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9f5fffd62702..574e5b8c6a65 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o endif ifdef CONFIG_SND_IMX_SOC