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ARM: Orion: CESA: Add support for clk

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Some orion platforms support gating of the clock. If the clock exists
enable/disbale it as appropriate.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Andrew Lunn 2012-02-19 11:56:19 +01:00 • committed by Mike Turquette
parent f4f7561e03
commit 1f80b126d0
2 changed files with 17 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/mach-kirkwood/common.c
View file

@ -87,6 +87,7 @@ static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
void __init kirkwood_clk_init(void) void __init kirkwood_clk_init(void)
{ {
struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio; struct clk *runit, *ge0, *ge1, *sata0, *sata1, *usb0, *sdio;
struct clk *crypto;
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
CLK_IS_ROOT, kirkwood_tclk); CLK_IS_ROOT, kirkwood_tclk);
@ -98,7 +99,7 @@ void __init kirkwood_clk_init(void)
sata1 = kirkwood_register_gate("sata1", CGC_BIT_SATA1); sata1 = kirkwood_register_gate("sata1", CGC_BIT_SATA1);
usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0); usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO); sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
kirkwood_register_gate("crypto", CGC_BIT_CRYPTO); crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
kirkwood_register_gate("xor0", CGC_BIT_XOR0); kirkwood_register_gate("xor0", CGC_BIT_XOR0);
kirkwood_register_gate("xor1", CGC_BIT_XOR1); kirkwood_register_gate("xor1", CGC_BIT_XOR1);
kirkwood_register_gate("pex0", CGC_BIT_PEX0); kirkwood_register_gate("pex0", CGC_BIT_PEX0);
@ -118,6 +119,7 @@ void __init kirkwood_clk_init(void)
orion_clkdev_add(NULL, "orion-ehci.0", usb0); orion_clkdev_add(NULL, "orion-ehci.0", usb0);
orion_clkdev_add(NULL, "orion_nand", runit); orion_clkdev_add(NULL, "orion_nand", runit);
orion_clkdev_add(NULL, "mvsdio", sdio); orion_clkdev_add(NULL, "mvsdio", sdio);
orion_clkdev_add(NULL, "mv_crypto", crypto);
} }
/***************************************************************************** /*****************************************************************************

14
drivers/crypto/mv_cesa.c
View file

@ -16,6 +16,7 @@
#include <linux/scatterlist.h> #include <linux/scatterlist.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/clk.h>
#include <crypto/internal/hash.h> #include <crypto/internal/hash.h>
#include <crypto/sha.h> #include <crypto/sha.h>
@ -79,6 +80,7 @@ struct crypto_priv {
void __iomem *reg; void __iomem *reg;
void __iomem *sram; void __iomem *sram;
int irq; int irq;
struct clk *clk;
struct task_struct *queue_th; struct task_struct *queue_th;
/* the lock protects queue and eng_st */ /* the lock protects queue and eng_st */
@ -1053,6 +1055,12 @@ static int mv_probe(struct platform_device *pdev)
if (ret) if (ret)
goto err_thread; goto err_thread;
/* Not all platforms can gate the clock, so it is not
an error if the clock does not exists. */
cp->clk = clk_get(&pdev->dev, NULL);
if (!IS_ERR(cp->clk))
clk_prepare_enable(cp->clk);
writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK); writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG); writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0); writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
@ -1118,6 +1126,12 @@ static int mv_remove(struct platform_device *pdev)
memset(cp->sram, 0, cp->sram_size); memset(cp->sram, 0, cp->sram_size);
iounmap(cp->sram); iounmap(cp->sram);
iounmap(cp->reg); iounmap(cp->reg);
if (!IS_ERR(cp->clk)) {
clk_disable_unprepare(cp->clk);
clk_put(cp->clk);
}
kfree(cp); kfree(cp);
cpg = NULL; cpg = NULL;
return 0; return 0;