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drm/radeon/kms/evergreen: set the clear state to the blit state

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The hw stores a default clear state for registers in the context
range that can be initialized when the CP is set up.  Set the
blit state as the default clear state and use the CLEAR_STATE
packet to load the blit state rather than loading it from an IB.
This reduces overhead when doing bo moves using the 3D engine.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2010-10-21 13:31:38 -04:00 • committed by Dave Airlie
parent c3cceeddf0
commit 2281a378e1
4 changed files with 65 additions and 54 deletions
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19
drivers/gpu/drm/radeon/evergreen_blit_shaders.c
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@ -39,10 +39,6 @@
const u32 evergreen_default_state[] =
{
0xc0012800, /* CONTEXT_CONTROL */
0x80000000,
0x80000000,
0xc0016900,
0x0000023b,
0x00000000, /* SQ_LDS_ALLOC_PS */
@ -63,17 +59,11 @@ const u32 evergreen_default_state[] =
0x00000000,
0x00000000,
0xc0026f00,
0x00000000,
0x00000000, /* SQ_VTX_BASE_VTX_LOC */
0x00000000,
0xc0026900,
0x00000010,
0x00000000, /* DB_Z_INFO */
0x00000000, /* DB_STENCIL_INFO */
0xc0016900,
0x00000200,
0x00000000, /* DB_DEPTH_CONTROL */
@ -303,11 +293,10 @@ const u32 evergreen_default_state[] =
0x00000000, /* */
0x00000000, /* */
0xc0036e00, /* SET_SAMPLER */
0x00000000,
0x00000012,
0x00000000,
0x00000000,
0xc0026900,
0x00000316,
0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
0x00000010, /* */
};
const u32 evergreen_vs[] =