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drm/tegra: dp: Turn link capabilities into booleans

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Rather than storing capabilities as flags in an integer, use a separate
boolean per capability. This simplifies the code that checks for these
capabilities.

Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding 2015-12-03 12:45:45 +01:00
parent c728e2d4a6
commit 27ba465ce3
3 changed files with 36 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

18
drivers/gpu/drm/tegra/dp.c
View file

@ -8,6 +8,17 @@
#include "dp.h" #include "dp.h"
static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
{
caps->enhanced_framing = false;
}
void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
const struct drm_dp_link_caps *src)
{
dest->enhanced_framing = src->enhanced_framing;
}
static void drm_dp_link_reset(struct drm_dp_link *link) static void drm_dp_link_reset(struct drm_dp_link *link)
{ {
if (!link) if (!link)
@ -16,7 +27,8 @@ static void drm_dp_link_reset(struct drm_dp_link *link)
link->revision = 0; link->revision = 0;
link->max_rate = 0; link->max_rate = 0;
link->max_lanes = 0; link->max_lanes = 0;
link->capabilities = 0;
drm_dp_link_caps_reset(&link->caps);
link->rate = 0; link->rate = 0;
link->lanes = 0; link->lanes = 0;
@ -49,7 +61,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
if (values[2] & DP_ENHANCED_FRAME_CAP) if (values[2] & DP_ENHANCED_FRAME_CAP)
link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; link->caps.enhanced_framing = true;
link->rate = link->max_rate; link->rate = link->max_rate;
link->lanes = link->max_lanes; link->lanes = link->max_lanes;
@ -139,7 +151,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
values[0] = drm_dp_link_rate_to_bw_code(link->rate); values[0] = drm_dp_link_rate_to_bw_code(link->rate);
values[1] = link->lanes; values[1] = link->lanes;
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) if (link->caps.enhanced_framing)
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));

22
drivers/gpu/drm/tegra/dp.h
View file

@ -7,16 +7,31 @@
#ifndef DRM_TEGRA_DP_H #ifndef DRM_TEGRA_DP_H
#define DRM_TEGRA_DP_H 1 #define DRM_TEGRA_DP_H 1
#include <linux/types.h>
struct drm_dp_aux; struct drm_dp_aux;
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) /**
* struct drm_dp_link_caps - DP link capabilities
*/
struct drm_dp_link_caps {
/**
* @enhanced_framing:
*
* enhanced framing capability (mandatory as of DP 1.2)
*/
bool enhanced_framing;
};
void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
const struct drm_dp_link_caps *src);
/** /**
* struct drm_dp_link - DP link capabilities and configuration * struct drm_dp_link - DP link capabilities and configuration
* @revision: DP specification revision supported on the link * @revision: DP specification revision supported on the link
* @max_rate: maximum clock rate supported on the link * @max_rate: maximum clock rate supported on the link
* @max_lanes: maximum number of lanes supported on the link * @max_lanes: maximum number of lanes supported on the link
* @capabilities: bitmask of capabilities supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps)
* @rate: currently configured link rate * @rate: currently configured link rate
* @lanes: currently configured number of lanes * @lanes: currently configured number of lanes
*/ */
@ -24,7 +39,8 @@ struct drm_dp_link {
unsigned char revision; unsigned char revision;
unsigned int max_rate; unsigned int max_rate;
unsigned int max_lanes; unsigned int max_lanes;
unsigned long capabilities;
struct drm_dp_link_caps caps;
unsigned int rate; unsigned int rate;
unsigned int lanes; unsigned int lanes;

4
drivers/gpu/drm/tegra/sor.c
View file

@ -977,7 +977,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
config->hblank_symbols = div_u64(num, pclk); config->hblank_symbols = div_u64(num, pclk);
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) if (link->caps.enhanced_framing)
config->hblank_symbols -= 3; config->hblank_symbols -= 3;
config->hblank_symbols -= 12 / link->lanes; config->hblank_symbols -= 12 / link->lanes;
@ -1918,7 +1918,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) if (link.caps.enhanced_framing)
value |= SOR_DP_LINKCTL_ENHANCED_FRAME; value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);