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net: hns3: Add "tc config" info query function

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This patch prints tc config information.

debugfs command:
echo dump tc > cmd

Sample Output:
root@(none)# echo dump tc > cmd
hns3 0000:7d:00.0: weight_offset: 14
hns3 0000:7d:00.0: tc(0): no sp mode
hns3 0000:7d:00.0: tc(1): no sp mode
hns3 0000:7d:00.0: tc(2): no sp mode
hns3 0000:7d:00.0: tc(3): no sp mode
hns3 0000:7d:00.0: tc(4): no sp mode
hns3 0000:7d:00.0: tc(5): no sp mode
hns3 0000:7d:00.0: tc(6): no sp mode
hns3 0000:7d:00.0: tc(7): no sp mode
root@(none)#

Signed-off-by: liuzhongzhu <liuzhongzhu@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
liuzhongzhu 2018-11-22 14:09:44 +00:00 • committed by David S. Miller
parent 3c666b586a
commit 2849d4e7a1
4 changed files with 48 additions and 0 deletions
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1
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
View file

@ -130,6 +130,7 @@ static void hns3_dbg_help(struct hnae3_handle *h)
dev_info(&h->pdev->dev, "available commands\n"); dev_info(&h->pdev->dev, "available commands\n");
dev_info(&h->pdev->dev, "queue info [number]\n"); dev_info(&h->pdev->dev, "queue info [number]\n");
dev_info(&h->pdev->dev, "dump fd tcam\n"); dev_info(&h->pdev->dev, "dump fd tcam\n");
dev_info(&h->pdev->dev, "dump tc\n");
} }
static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer, static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,

1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View file

@ -126,6 +126,7 @@ enum hclge_opcode_type {
HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
/* Packet buffer allocate commands */ /* Packet buffer allocate commands */
HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,

40
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
View file

@ -5,8 +5,46 @@
#include "hclge_cmd.h" #include "hclge_cmd.h"
#include "hclge_main.h" #include "hclge_main.h"
#include "hclge_tm.h"
#include "hnae3.h" #include "hnae3.h"
static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index,
char *title_buf, char *true_buf,
char *false_buf)
{
if (flag)
dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index,
true_buf);
else
dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index,
false_buf);
}
static void hclge_dbg_dump_tc(struct hclge_dev *hdev)
{
struct hclge_ets_tc_weight_cmd *ets_weight;
struct hclge_desc desc;
int i, ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "dump tc fail, status is %d.\n", ret);
return;
}
ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
dev_info(&hdev->pdev->dev, "dump tc\n");
dev_info(&hdev->pdev->dev, "weight_offset: %u\n",
ets_weight->weight_offset);
for (i = 0; i < HNAE3_MAX_TC; i++)
hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i,
"tc", "no sp mode", "sp mode");
}
static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage, static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage,
bool sel_x, u32 loc) bool sel_x, u32 loc)
{ {
@ -68,6 +106,8 @@ int hclge_dbg_run_cmd(struct hnae3_handle *handle, char *cmd_buf)
if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) { if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) {
hclge_dbg_fd_tcam(hdev); hclge_dbg_fd_tcam(hdev);
} else if (strncmp(cmd_buf, "dump tc", 7) == 0) {
hclge_dbg_dump_tc(hdev);
} else { } else {
dev_info(&hdev->pdev->dev, "unknown command\n"); dev_info(&hdev->pdev->dev, "unknown command\n");
return -EINVAL; return -EINVAL;

6
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
View file

@ -55,6 +55,12 @@ struct hclge_qs_weight_cmd {
u8 dwrr; u8 dwrr;
}; };
struct hclge_ets_tc_weight_cmd {
u8 tc_weight[HNAE3_MAX_TC];
u8 weight_offset;
u8 rsvd[15];
};
#define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0) #define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0)
#define HCLGE_TM_SHAP_IR_B_LSH 0 #define HCLGE_TM_SHAP_IR_B_LSH 0
#define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8) #define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8)