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- Add a quirk for AMD Zen machines where Instruction Fetch unit poison
consumption MCEs are not delivered synchronously but still within the same context, which can lead to erroneously increased error severity and unneeded kernel panics - Do not log errors caught by polling shared MCA banks as they materialize as duplicated error records otherwise -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmTsNcoACgkQEsHwGGHe VUq4MBAApcFUWxsA8co+v235W05mqAvsb8pt4RLFCYBQ6INCKFPMwP3ShEjSgnvZ owQdPC2j7qzUiMFeDmBn1GXoENgv/Azc1A/0AKa5tKctHrS1Z/ZvDBncydY1HzTu o4JYRN+KQWoaf0Nz8iYgBNjblPxw057Lg4fmOyCu1F6mmWypdBjC43fGoDTdTIZd 4uhxVzS09ns1GhBpDoJbj6SXSpbOtvnMguGVrXvuhw+NBfaYpJ6Fb5gH2TrT8rWE jd5uSOSxYVPIjt5XjLfhu2eQheecJiYIxTWbNlVRUZHgmvVgtRon5WwMVSrFxJL2 vLawaKvnHjgsOIewW0d9hEe6PVgvcUEMwQNmI86vDzCi+RGM8pbRZYqCInYyDtBd e6W1ZsfqVBWO9LKr7T9LEMM7HlGSe8aPkaeTfmCv18+hgvEkkjXY19dcLYe+ExmW 2JvsxF08wqXPAIBDy7cN4DHWdRTd3g91Qd10Ex6bUMovifP9Jt3KXWAuX7qWPjY2 YvLASs/04z5sGNk3XB+f2EOPMJRHjHneNppQLuSBIzhOFXOHDA70aObNGfXw8oGK fGhPTEXFJWhTH7fL7FZCwGEEARXkuOWBpIX1HNYst2zFwKNTNqzaxkxAMYwdv6j5 K30hNMrCQj912t82NWOoerPt0uRLdXDKKTJV0VJNfcP8oaA3nec= =RMCN -----END PGP SIGNATURE----- Merge tag 'ras_core_for_v6.6_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 RAS updates from Borislav Petkov: - Add a quirk for AMD Zen machines where Instruction Fetch unit poison consumption MCEs are not delivered synchronously but still within the same context, which can lead to erroneously increased error severity and unneeded kernel panics - Do not log errors caught by polling shared MCA banks as they materialize as duplicated error records otherwise * tag 'ras_core_for_v6.6_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/MCE: Always save CS register on AMD Zen IF Poison errors x86/mce: Prevent duplicate error records
This commit is contained in:
commit
28c59d9421
3 changed files with 57 additions and 3 deletions
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@ -842,6 +842,26 @@ static noinstr bool quirk_skylake_repmov(void)
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return false;
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}
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/*
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* Some Zen-based Instruction Fetch Units set EIPV=RIPV=0 on poison consumption
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* errors. This means mce_gather_info() will not save the "ip" and "cs" registers.
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*
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* However, the context is still valid, so save the "cs" register for later use.
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*
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* The "ip" register is truly unknown, so don't save it or fixup EIPV/RIPV.
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*
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* The Instruction Fetch Unit is at MCA bank 1 for all affected systems.
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*/
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static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs)
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{
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if (bank != 1)
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return;
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if (!(m->status & MCI_STATUS_POISON))
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return;
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m->cs = regs->cs;
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}
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/*
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* Do a quick check if any of the events requires a panic.
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* This decides if we keep the events around or clear them.
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@ -861,6 +881,9 @@ static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned lo
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if (mce_flags.snb_ifu_quirk)
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quirk_sandybridge_ifu(i, m, regs);
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if (mce_flags.zen_ifu_quirk)
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quirk_zen_ifu(i, m, regs);
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m->bank = i;
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if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
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mce_read_aux(m, i);
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@ -1608,6 +1631,13 @@ static void __start_timer(struct timer_list *t, unsigned long interval)
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local_irq_restore(flags);
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}
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static void mc_poll_banks_default(void)
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{
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machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
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}
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void (*mc_poll_banks)(void) = mc_poll_banks_default;
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static void mce_timer_fn(struct timer_list *t)
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{
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struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
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@ -1618,7 +1648,7 @@ static void mce_timer_fn(struct timer_list *t)
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iv = __this_cpu_read(mce_next_interval);
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if (mce_available(this_cpu_ptr(&cpu_info))) {
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machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
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mc_poll_banks();
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if (mce_intel_cmci_poll()) {
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iv = mce_adjust_timer(iv);
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@ -1842,6 +1872,9 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
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if (c->x86 == 0x15 && c->x86_model <= 0xf)
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mce_flags.overflow_recov = 1;
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if (c->x86 >= 0x17 && c->x86 <= 0x1A)
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mce_flags.zen_ifu_quirk = 1;
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}
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if (c->x86_vendor == X86_VENDOR_INTEL) {
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@ -56,6 +56,13 @@ static DEFINE_PER_CPU(int, cmci_backoff_cnt);
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*/
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static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
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/*
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* On systems that do support CMCI but it's disabled, polling for MCEs can
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* cause the same event to be reported multiple times because IA32_MCi_STATUS
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* is shared by the same package.
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*/
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static DEFINE_SPINLOCK(cmci_poll_lock);
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#define CMCI_THRESHOLD 1
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#define CMCI_POLL_INTERVAL (30 * HZ)
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#define CMCI_STORM_INTERVAL (HZ)
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@ -426,12 +433,22 @@ void cmci_disable_bank(int bank)
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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/* Bank polling function when CMCI is disabled. */
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static void cmci_mc_poll_banks(void)
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{
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spin_lock(&cmci_poll_lock);
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machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
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spin_unlock(&cmci_poll_lock);
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}
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void intel_init_cmci(void)
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{
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int banks;
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if (!cmci_supported(&banks))
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if (!cmci_supported(&banks)) {
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mc_poll_banks = cmci_mc_poll_banks;
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return;
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}
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mce_threshold_vector = intel_threshold_interrupt;
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cmci_discover(banks);
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@ -157,6 +157,9 @@ struct mce_vendor_flags {
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*/
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smca : 1,
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/* Zen IFU quirk */
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zen_ifu_quirk : 1,
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/* AMD-style error thresholding banks present. */
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amd_threshold : 1,
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@ -172,7 +175,7 @@ struct mce_vendor_flags {
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/* Skylake, Cascade Lake, Cooper Lake REP;MOVS* quirk */
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skx_repmov_quirk : 1,
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__reserved_0 : 56;
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__reserved_0 : 55;
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};
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extern struct mce_vendor_flags mce_flags;
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@ -274,4 +277,5 @@ static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
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return 0;
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}
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extern void (*mc_poll_banks)(void);
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#endif /* __X86_MCE_INTERNAL_H__ */
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