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- Add a quirk for AMD Zen machines where Instruction Fetch unit poison

Browse source 
consumption MCEs are not delivered synchronously but still within the
   same context, which can lead to erroneously increased error severity
   and unneeded kernel panics
 
 - Do not log errors caught by polling shared MCA banks as they
   materialize as duplicated error records otherwise
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Merge tag 'ras_core_for_v6.6_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 RAS updates from Borislav Petkov:

 - Add a quirk for AMD Zen machines where Instruction Fetch unit poison
   consumption MCEs are not delivered synchronously but still within the
   same context, which can lead to erroneously increased error severity
   and unneeded kernel panics

 - Do not log errors caught by polling shared MCA banks as they
   materialize as duplicated error records otherwise

* tag 'ras_core_for_v6.6_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/MCE: Always save CS register on AMD Zen IF Poison errors
  x86/mce: Prevent duplicate error records
This commit is contained in:
Linus Torvalds 2023-08-28 15:23:07 -07:00
commit 28c59d9421
3 changed files with 57 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
arch/x86/kernel/cpu/mce/core.c
View file

@ -842,6 +842,26 @@ static noinstr bool quirk_skylake_repmov(void)
return false;
}
/*
* Some Zen-based Instruction Fetch Units set EIPV=RIPV=0 on poison consumption
* errors. This means mce_gather_info() will not save the "ip" and "cs" registers.
*
* However, the context is still valid, so save the "cs" register for later use.
*
* The "ip" register is truly unknown, so don't save it or fixup EIPV/RIPV.
*
* The Instruction Fetch Unit is at MCA bank 1 for all affected systems.
*/
static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs)
{
if (bank != 1)
return;
if (!(m->status & MCI_STATUS_POISON))
return;
m->cs = regs->cs;
}
/*
* Do a quick check if any of the events requires a panic.
* This decides if we keep the events around or clear them.
@ -861,6 +881,9 @@ static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned lo
if (mce_flags.snb_ifu_quirk)
quirk_sandybridge_ifu(i, m, regs);
if (mce_flags.zen_ifu_quirk)
quirk_zen_ifu(i, m, regs);
m->bank = i;
if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
mce_read_aux(m, i);
@ -1608,6 +1631,13 @@ static void __start_timer(struct timer_list *t, unsigned long interval)
local_irq_restore(flags);
}
static void mc_poll_banks_default(void)
{
machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
}
void (*mc_poll_banks)(void) = mc_poll_banks_default;
static void mce_timer_fn(struct timer_list *t)
{
struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
@ -1618,7 +1648,7 @@ static void mce_timer_fn(struct timer_list *t)
iv = __this_cpu_read(mce_next_interval);
if (mce_available(this_cpu_ptr(&cpu_info))) {
machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
mc_poll_banks();
if (mce_intel_cmci_poll()) {
iv = mce_adjust_timer(iv);
@ -1842,6 +1872,9 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
if (c->x86 == 0x15 && c->x86_model <= 0xf)
mce_flags.overflow_recov = 1;
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
mce_flags.zen_ifu_quirk = 1;
}
if (c->x86_vendor == X86_VENDOR_INTEL) {

19
arch/x86/kernel/cpu/mce/intel.c
View file

@ -56,6 +56,13 @@ static DEFINE_PER_CPU(int, cmci_backoff_cnt);
*/
static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
/*
* On systems that do support CMCI but it's disabled, polling for MCEs can
* cause the same event to be reported multiple times because IA32_MCi_STATUS
* is shared by the same package.
*/
static DEFINE_SPINLOCK(cmci_poll_lock);
#define CMCI_THRESHOLD 1
#define CMCI_POLL_INTERVAL (30 * HZ)
#define CMCI_STORM_INTERVAL (HZ)
@ -426,12 +433,22 @@ void cmci_disable_bank(int bank)
raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
}
/* Bank polling function when CMCI is disabled. */
static void cmci_mc_poll_banks(void)
{
spin_lock(&cmci_poll_lock);
machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
spin_unlock(&cmci_poll_lock);
}
void intel_init_cmci(void)
{
int banks;
if (!cmci_supported(&banks))
if (!cmci_supported(&banks)) {
mc_poll_banks = cmci_mc_poll_banks;
return;
}
mce_threshold_vector = intel_threshold_interrupt;
cmci_discover(banks);

6
arch/x86/kernel/cpu/mce/internal.h
View file

@ -157,6 +157,9 @@ struct mce_vendor_flags {
*/
smca : 1,
/* Zen IFU quirk */
zen_ifu_quirk : 1,
/* AMD-style error thresholding banks present. */
amd_threshold : 1,
@ -172,7 +175,7 @@ struct mce_vendor_flags {
/* Skylake, Cascade Lake, Cooper Lake REP;MOVS* quirk */
skx_repmov_quirk : 1,
__reserved_0 : 56;
__reserved_0 : 55;
};
extern struct mce_vendor_flags mce_flags;
@ -274,4 +277,5 @@ static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
return 0;
}
extern void (*mc_poll_banks)(void);
#endif /* __X86_MCE_INTERNAL_H__ */