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spi: sh-msiof: Configure MSIOF sync signal timing in device tree
The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So,
this patch adds new properties like the following commit:
d0fb47a523
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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3 changed files with 65 additions and 0 deletions
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@ -7,6 +7,8 @@ struct sh_msiof_spi_info {
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u16 num_chipselect;
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unsigned int dma_tx_id;
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unsigned int dma_rx_id;
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u32 dtdl;
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u32 syncdl;
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};
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#endif /* __SPI_SH_MSIOF_H__ */
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