spi: sh-msiof: Configure MSIOF sync signal timing in device tree

The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So,
this patch adds new properties like the following commit:
  d0fb47a523
  (spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Yoshihiro Shimoda 2014-12-19 17:15:53 +09:00 committed by Mark Brown
parent 97bf6af1f9
commit 3110628d89
3 changed files with 65 additions and 0 deletions

View file

@ -7,6 +7,8 @@ struct sh_msiof_spi_info {
u16 num_chipselect;
unsigned int dma_tx_id;
unsigned int dma_rx_id;
u32 dtdl;
u32 syncdl;
};
#endif /* __SPI_SH_MSIOF_H__ */