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i.MX fixes for 6.2:

Browse source 
- Fix i.MX8MP DT for missing GPC Interrupt, power-domain typo and USB
   clock error.
 - Fix mach-imx cpu code to add missing of_node_put() call.
 - A couple of verdin-imx8mm DT fixes for audio playback support.
 - Fix pca9547 i2c-mux node name for i.MX and Vybrid device trees.
 - Fix an imx93-11x11-evk uSDHC pad setting problem that causes Micron
   eMMC CMD8 CRC error in HS400ES/HS400 mode.
 - A couple of imx8mp-blk-ctrl driver fixes from Lucas Stach, enabling
   pixclk with HDMI_TX_PHY PD, dropping power device name setting.
 - Fix the error check for of_clk_get_by_name() in soc-imx8m driver.
 - Other various DT fixes and cleanups.
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Merge tag 'imx-fixes-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 6.2:

- Fix i.MX8MP DT for missing GPC Interrupt, power-domain typo and USB
  clock error.
- Fix mach-imx cpu code to add missing of_node_put() call.
- A couple of verdin-imx8mm DT fixes for audio playback support.
- Fix pca9547 i2c-mux node name for i.MX and Vybrid device trees.
- Fix an imx93-11x11-evk uSDHC pad setting problem that causes Micron
  eMMC CMD8 CRC error in HS400ES/HS400 mode.
- A couple of imx8mp-blk-ctrl driver fixes from Lucas Stach, enabling
  pixclk with HDMI_TX_PHY PD, dropping power device name setting.
- Fix the error check for of_clk_get_by_name() in soc-imx8m driver.
- Other various DT fixes and cleanups.

* tag 'imx-fixes-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (22 commits)
  soc: imx8m: Fix incorrect check for of_clk_get_by_name()
  arm64: dts: imx8mm-venice-gw7901: fix USB2 controller OC polarity
  arm64: dts: imx8mp-evk: pcie0-refclk cosmetic cleanup
  arm64: dts: imx8mp: Fix power-domain typo
  arm64: dts: imx8mp: Fix missing GPC Interrupt
  soc: imx: imx8mp-blk-ctrl: don't set power device name
  arm64: dts: imx8mm: Drop xtal clock specifier from eDM SBC
  ARM: imx: add missing of_node_put()
  arm64: dts: imx93-11x11-evk: correct clock and strobe pad setting
  arm64: dts: verdin-imx8mm: fix dev board audio playback
  arm64: dts: imx8mq-thor96: fix no-mmc property for SDHCI
  arm64: dts: imx8mm-beacon: Fix ecspi2 pinmux
  arm64: dts: freescale: Fix pca954x i2c-mux node names
  ARM: dts: vf610: Fix pca9548 i2c-mux node names
  ARM: dts: imx: Fix pca9547 i2c-mux node name
  arm64: dts: verdin-imx8mm: fix dahlia audio playback
  ARM: dts: imx6qdl-gw560x: Remove incorrect 'uart-has-rtscts'
  ARM: dts: imx7d-pico: Use 'clock-frequency'
  ARM: dts: imx6ul-pico-dwarf: Use 'clock-frequency'
  arm64: dts: imx8mp-phycore-som: Remove invalid PMIC property
  ...

Link: https://lore.kernel.org/r/20230102132016.GA10699@T480
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-01-09 23:16:38 +01:00
commit 33abcaef98
36 changed files with 53 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/boot/dts/imx53-ppd.dts
View file

@ -488,7 +488,7 @@
scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
View file

@ -632,7 +632,6 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};

2
arch/arm/boot/dts/imx6ul-pico-dwarf.dts
View file

@ -32,7 +32,7 @@
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";

4
arch/arm/boot/dts/imx7d-pico-dwarf.dts
View file

@ -32,7 +32,7 @@
};
&i2c1 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
@ -52,7 +52,7 @@
};
&i2c4 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";

4
arch/arm/boot/dts/imx7d-pico-nymph.dts
View file

@ -43,7 +43,7 @@
};
&i2c1 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
@ -64,7 +64,7 @@
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";

2
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
View file

@ -345,7 +345,7 @@
};
&i2c2 {
tca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
pinctrl-names = "default";

2
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
View file

@ -340,7 +340,7 @@
};
&i2c2 {
tca9548@70 {
i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
pinctrl-names = "default";

1
arch/arm/mach-imx/cpu-imx25.c
View file

@ -23,6 +23,7 @@ static int mx25_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
rev = readl(iim_base + MXC_IIMSREV);
iounmap(iim_base);

1
arch/arm/mach-imx/cpu-imx27.c
View file

@ -28,6 +28,7 @@ static int mx27_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
ccm_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!ccm_base);
/*
* now we have access to the IO registers. As we need

1
arch/arm/mach-imx/cpu-imx31.c
View file

@ -39,6 +39,7 @@ static int mx31_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
/* read SREV register from IIM module */

1
arch/arm/mach-imx/cpu-imx35.c
View file

@ -21,6 +21,7 @@ static int mx35_read_cpu_rev(void)
np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
rev = imx_readl(iim_base + MXC_IIMSREV);

1
arch/arm/mach-imx/cpu-imx5.c
View file

@ -28,6 +28,7 @@ static u32 imx5_read_srev_reg(const char *compat)
np = of_find_compatible_node(NULL, NULL, compat);
iim_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!iim_base);
srev = readl(iim_base + IIM_SREV) & 0xff;

2
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View file

@ -110,7 +110,7 @@
&i2c0 {
status = "okay";
pca9547@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View file

@ -89,7 +89,7 @@
&i2c0 {
status = "okay";
pca9547@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View file

@ -88,7 +88,7 @@
&i2c0 {
status = "okay";
pca9547@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
View file

@ -53,7 +53,7 @@
&i2c0 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
View file

@ -136,7 +136,7 @@
&i2c0 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
View file

@ -245,7 +245,7 @@
&i2c3 {
status = "okay";
i2c-switch@70 {
i2c-mux@70 {
compatible = "nxp,pca9540";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
View file

@ -103,7 +103,7 @@
&i2c0 {
status = "okay";
pca9547@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
View file

@ -44,7 +44,7 @@
&i2c0 {
status = "okay";
pca9547@75 {
i2c-mux@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View file

@ -54,7 +54,7 @@
&i2c0 {
status = "okay";
i2c-switch@77 {
i2c-mux@77 {
compatible = "nxp,pca9547";
#address-cells = <1>;
#size-cells = <0>;

4
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View file

@ -120,7 +120,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {
@ -316,7 +316,7 @@
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
>;
};

2
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
View file

@ -275,7 +275,7 @@
compatible = "rohm,bd71847";
reg = <0x4b>;
#clock-cells = <0>;
clocks = <&clk_xtal32k 0>;
clocks = <&clk_xtal32k>;
clock-output-names = "clk-32k-out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;

2
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
View file

@ -214,7 +214,7 @@
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
i2cmux@70 {
i2c-mux@70 {
compatible = "nxp,pca9540";
reg = <0x70>;
#address-cells = <1>;

1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View file

@ -771,6 +771,7 @@
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb2_vbus>;
over-current-active-low;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
View file

@ -9,6 +9,7 @@
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",

1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
View file

@ -11,6 +11,7 @@
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",

4
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View file

@ -36,8 +36,8 @@
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_can1_stby: regulator-can1-stby {

10
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View file

@ -99,7 +99,6 @@
regulators {
buck1: BUCK1 {
regulator-compatible = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
@ -108,7 +107,6 @@
};
buck2: BUCK2 {
regulator-compatible = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
@ -119,7 +117,6 @@
};
buck4: BUCK4 {
regulator-compatible = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@ -127,7 +124,6 @@
};
buck5: BUCK5 {
regulator-compatible = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@ -135,7 +131,6 @@
};
buck6: BUCK6 {
regulator-compatible = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
@ -143,7 +138,6 @@
};
ldo1: LDO1 {
regulator-compatible = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@ -151,7 +145,6 @@
};
ldo2: LDO2 {
regulator-compatible = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
@ -159,7 +152,6 @@
};
ldo3: LDO3 {
regulator-compatible = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@ -167,13 +159,11 @@
};
ldo4: LDO4 {
regulator-compatible = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo5: LDO5 {
regulator-compatible = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;

15
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file

@ -524,6 +524,7 @@
compatible = "fsl,imx8mp-gpc";
reg = <0x303a0000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
@ -590,7 +591,7 @@
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
};
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
@ -1297,7 +1298,7 @@
reg = <0x32f10100 0x8>,
<0x381f0000 0x20>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@ -1310,9 +1311,9 @@
usb_dwc3_0: usb@38100000 {
compatible = "snps,dwc3";
reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
@ -1339,7 +1340,7 @@
reg = <0x32f10108 0x8>,
<0x382f0000 0x20>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@ -1352,9 +1353,9 @@
usb_dwc3_1: usb@38200000 {
compatible = "snps,dwc3";
reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;

4
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
View file

@ -133,7 +133,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2cmux@70 {
i2c-mux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
@ -216,7 +216,7 @@
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pca9546: i2cmux@70 {
pca9546: i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;

4
arch/arm64/boot/dts/freescale/imx8mq-thor96.dts
View file

@ -339,7 +339,7 @@
bus-width = <4>;
non-removable;
no-sd;
no-emmc;
no-mmc;
status = "okay";
brcmf: wifi@1 {
@ -359,7 +359,7 @@
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-sdio;
no-emmc;
no-mmc;
disable-wp;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View file

@ -61,7 +61,7 @@
pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
status = "okay";
i2c-switch@71 {
i2c-mux@71 {
compatible = "nxp,pca9646", "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View file

@ -74,7 +74,7 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
@ -84,7 +84,7 @@
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
@ -102,7 +102,7 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe

7
drivers/soc/imx/imx8mp-blk-ctrl.c
View file

@ -212,7 +212,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
break;
case IMX8MP_HDMIBLK_PD_LCDIF:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
@ -241,6 +241,7 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
break;
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
@ -270,7 +271,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
BIT(4) | BIT(5) | BIT(6));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
BIT(16) | BIT(17) | BIT(18) |
BIT(19) | BIT(20));
break;
case IMX8MP_HDMIBLK_PD_PAI:
@ -298,6 +299,7 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
break;
case IMX8MP_HDMIBLK_PD_HDCP:
@ -590,7 +592,6 @@ static int imx8mp_blk_ctrl_probe(struct platform_device *pdev)
ret = PTR_ERR(domain->power_dev);
goto cleanup_pds;
}
dev_set_name(domain->power_dev, "%s", data->name);
domain->genpd.name = data->name;
domain->genpd.power_on = imx8mp_blk_ctrl_power_on;

4
drivers/soc/imx/soc-imx8m.c
View file

@ -66,8 +66,8 @@ static u32 __init imx8mq_soc_revision(void)
ocotp_base = of_iomap(np, 0);
WARN_ON(!ocotp_base);
clk = of_clk_get_by_name(np, NULL);
if (!clk) {
WARN_ON(!clk);
if (IS_ERR(clk)) {
WARN_ON(IS_ERR(clk));
return 0;
}