mirror of
https://github.com/Fishwaldo/Star64_linux.git
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dmaengine: Add dw-axi-dmac-starfive driver for JH7100
This commit is contained in:
parent
57e4b6e737
commit
34a3438954
6 changed files with 652 additions and 0 deletions
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@ -181,6 +181,13 @@ config DW_AXI_DMAC
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NOTE: This driver wasn't tested on 64 bit platform because
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of lack 64 bit platform with Synopsys DW AXI DMAC.
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config DW_AXI_DMAC_STARFIVE
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tristate "Synopsys DesignWare AXI DMA support for StarFive SOC"
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depends on SOC_STARFIVE
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help
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Enable support for Synopsys DesignWare AXI DMA controller.
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NOTE: It's for StarFive SOC.
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config EP93XX_DMA
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bool "Cirrus Logic EP93xx DMA support"
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depends on ARCH_EP93XX || COMPILE_TEST
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@ -27,6 +27,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o
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obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
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obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
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obj-$(CONFIG_DW_AXI_DMAC_STARFIVE) += dw-axi-dmac-starfive/
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obj-$(CONFIG_DW_DMAC_CORE) += dw/
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obj-$(CONFIG_DW_EDMA) += dw-edma/
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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2
drivers/dma/dw-axi-dmac-starfive/Makefile
Normal file
2
drivers/dma/dw-axi-dmac-starfive/Makefile
Normal file
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_DW_AXI_DMAC_STARFIVE) += starfive_dmaengine_memcpy.o dw-axi-dmac-starfive-misc.o
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323
drivers/dma/dw-axi-dmac-starfive/dw-axi-dmac-starfive-misc.c
Normal file
323
drivers/dma/dw-axi-dmac-starfive/dw-axi-dmac-starfive-misc.c
Normal file
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@ -0,0 +1,323 @@
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/*
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* Copyright 2020 StarFive, Inc <samin.guo@starfivetech.com>
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*
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* DW AXI dma driver for StarFive SoC VIC7100.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/uaccess.h>
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#include <linux/dmaengine.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <soc/sifive/sifive_l2_cache.h>
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#include <soc/starfive/jh7100_dma.h>
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#define DRIVER_NAME "dwaxidma"
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#define AXIDMA_IOC_MAGIC 'A'
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#define AXIDMA_IOCGETCHN _IO(AXIDMA_IOC_MAGIC, 0)
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#define AXIDMA_IOCCFGANDSTART _IO(AXIDMA_IOC_MAGIC, 1)
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#define AXIDMA_IOCGETSTATUS _IO(AXIDMA_IOC_MAGIC, 2)
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#define AXIDMA_IOCRELEASECHN _IO(AXIDMA_IOC_MAGIC, 3)
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#define AXI_DMA_MAX_CHANS 20
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#define DMA_CHN_UNUSED 0
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#define DMA_CHN_USED 1
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#define DMA_STATUS_UNFINISHED 0
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#define DMA_STATUS_FINISHED 1
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/* for DEBUG*/
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//#define DW_DMA_CHECK_RESULTS
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//#define DW_DMA_PRINT_MEM
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//#define DW_DMA_FLUSH_DESC
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struct axidma_chncfg {
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unsigned long src_addr; /*dma addr*/
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unsigned long dst_addr; /*dma addr*/
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unsigned long virt_src; /*mmap src addr*/
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unsigned long virt_dst; /*mmap dst addr*/
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unsigned long phys; /*desc phys addr*/
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unsigned int len; /*transport lenth*/
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int mem_fd; /*fd*/
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unsigned char chn_num; /*dma channels number*/
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unsigned char status; /*dma transport status*/
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};
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struct axidma_chns {
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struct dma_chan *dma_chan;
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unsigned char used;
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unsigned char status;
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unsigned char reserve[2];
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};
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struct axidma_chns channels[AXI_DMA_MAX_CHANS];
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#ifdef DW_DMA_PRINT_MEM
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void print_in_line_u64(u8 *p_name, u64 *p_buf, u32 len)
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{
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u32 i, j;
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u32 line;
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u32* ptmp;
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u32 len_tmp;
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u32 rest = len / 4;
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printk("%s: 0x%#llx, 0x%x\n",
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p_name, dw_virt_to_phys((void *)p_buf), len);
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if(len >= 0x1000)
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len_tmp = 0x1000 / 32; //print 128 size of memory.
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else
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len_tmp = len / 8; //print real 100% size of memory.
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rest = len / 4; //one line print 8 u32
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for (i = 0; i < len_tmp; i += 4, rest -= line) {
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if (!(i % 4))
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printk(KERN_CONT KERN_INFO" %#llx: ",
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dw_virt_to_phys((void *)(p_buf + i)));
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ptmp = (u32*)(p_buf + i);
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line = (rest > 8) ? 8 : rest;
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for (j = 0; j < line; j++)
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printk(KERN_CONT KERN_INFO "%08x ", *(ptmp + j));
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printk(KERN_CONT KERN_INFO"\n");
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}
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}
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#endif
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static int axidma_open(struct inode *inode, struct file *file)
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{
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/*Open: do nothing*/
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return 0;
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}
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static int axidma_release(struct inode *inode, struct file *file)
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{
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/* Release: do nothing */
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return 0;
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}
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static ssize_t axidma_write(struct file *file, const char __user *data,
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size_t len, loff_t *ppos)
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{
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/* Write: do nothing */
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return 0;
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}
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static void dma_complete_func(void *status)
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{
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*(char *)status = DMA_STATUS_FINISHED;
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}
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static long axidma_unlocked_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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int i, ret;
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dma_cap_mask_t mask;
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dma_cookie_t cookie;
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struct dma_device *dma_dev;
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struct axidma_chncfg chncfg;
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struct dma_async_tx_descriptor *tx;
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#ifdef DW_DMA_FLUSH_DESC
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void *des_chncfg = &chncfg;
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chncfg.phys = dw_virt_to_phys(des_chncfg);
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#endif
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memset(&chncfg, 0, sizeof(struct axidma_chncfg));
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switch(cmd) {
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case AXIDMA_IOCGETCHN:
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for(i = 0; i < AXI_DMA_MAX_CHANS; i++) {
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if(DMA_CHN_UNUSED == channels[i].used)
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break;
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}
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if(AXI_DMA_MAX_CHANS == i) {
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printk("Get dma chn failed, because no idle channel\n");
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goto error;
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} else {
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channels[i].used = DMA_CHN_USED;
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channels[i].status = DMA_STATUS_UNFINISHED;
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chncfg.status = DMA_STATUS_UNFINISHED;
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chncfg.chn_num = i;
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}
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dma_cap_zero(mask);
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dma_cap_set(DMA_MEMCPY, mask);
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channels[i].dma_chan = dma_request_channel(mask, NULL, NULL);
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if(!channels[i].dma_chan) {
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printk("dma request channel failed\n");
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channels[i].used = DMA_CHN_UNUSED;
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goto error;
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}
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ret = copy_to_user((void __user *)arg, &chncfg,
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sizeof(struct axidma_chncfg));
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if(ret) {
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printk("Copy to user failed\n");
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goto error;
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}
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break;
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case AXIDMA_IOCCFGANDSTART:
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#ifdef DW_DMA_CHECK_RESULTS
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void *src,*dst;
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#endif
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ret = copy_from_user(&chncfg, (void __user *)arg,
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sizeof(struct axidma_chncfg));
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if(ret) {
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printk("Copy from user failed\n");
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goto error;
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}
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if((chncfg.chn_num >= AXI_DMA_MAX_CHANS) ||
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(!channels[chncfg.chn_num].dma_chan)) {
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printk("chn_num[%d] is invalid\n", chncfg.chn_num);
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goto error;
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}
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dma_dev = channels[chncfg.chn_num].dma_chan->device;
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#ifdef DW_DMA_FLUSH_DESC
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sifive_l2_flush64_range(chncfg.phys,sizeof(chncfg));
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#endif
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#ifdef DW_DMA_CHECK_RESULTS
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src = dw_phys_to_virt(chncfg.src_addr);
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dst = dw_phys_to_virt(chncfg.dst_addr);
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#endif
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sifive_l2_flush64_range(chncfg.src_addr, chncfg.len);
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tx = dma_dev->device_prep_dma_memcpy(
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channels[chncfg.chn_num].dma_chan,
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chncfg.dst_addr, chncfg.src_addr, chncfg.len,
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DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
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if(!tx){
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printk("Failed to prepare DMA memcpy\n");
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goto error;
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}
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channels[chncfg.chn_num].status = DMA_STATUS_UNFINISHED;
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tx->callback_param = &channels[chncfg.chn_num].status;
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tx->callback = dma_complete_func;
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cookie = tx->tx_submit(tx);
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if(dma_submit_error(cookie)) {
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printk("Failed to dma tx_submit\n");
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goto error;
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}
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dma_async_issue_pending(channels[chncfg.chn_num].dma_chan);
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/*flush dcache*/
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sifive_l2_flush64_range(chncfg.dst_addr, chncfg.len);
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#ifdef DW_DMA_PRINT_MEM
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print_in_line_u64((u8 *)"src", (u64 *)src, chncfg.len);
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print_in_line_u64((u8 *)"dst", (u64 *)dst, chncfg.len);
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#endif
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#ifdef DW_DMA_CHECK_RESULTS
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if(memcmp(src, dst, chncfg.len))
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printk("check data faild.\n");
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else
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printk("check data ok.\n");
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#endif
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break;
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case AXIDMA_IOCGETSTATUS:
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ret = copy_from_user(&chncfg, (void __user *)arg,
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sizeof(struct axidma_chncfg));
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if(ret) {
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printk("Copy from user failed\n");
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goto error;
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}
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if(chncfg.chn_num >= AXI_DMA_MAX_CHANS) {
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printk("chn_num[%d] is invalid\n", chncfg.chn_num);
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goto error;
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}
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chncfg.status = channels[chncfg.chn_num].status;
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ret = copy_to_user((void __user *)arg, &chncfg,
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sizeof(struct axidma_chncfg));
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if(ret) {
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printk("Copy to user failed\n");
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goto error;
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}
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break;
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case AXIDMA_IOCRELEASECHN:
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ret = copy_from_user(&chncfg, (void __user *)arg,
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sizeof(struct axidma_chncfg));
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if(ret) {
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printk("Copy from user failed\n");
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goto error;
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}
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if((chncfg.chn_num >= AXI_DMA_MAX_CHANS) ||
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(!channels[chncfg.chn_num].dma_chan)) {
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printk("chn_num[%d] is invalid\n", chncfg.chn_num);
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goto error;
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}
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dma_release_channel(channels[chncfg.chn_num].dma_chan);
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channels[chncfg.chn_num].used = DMA_CHN_UNUSED;
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channels[chncfg.chn_num].status = DMA_STATUS_UNFINISHED;
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break;
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default:
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printk("Don't support cmd [%d]\n", cmd);
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break;
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}
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return 0;
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error:
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return -EFAULT;
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}
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/*
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* Kernel Interfaces
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*/
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static struct file_operations axidma_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = axidma_write,
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.unlocked_ioctl = axidma_unlocked_ioctl,
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.open = axidma_open,
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.release = axidma_release,
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};
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static struct miscdevice axidma_miscdev = {
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.minor = MISC_DYNAMIC_MINOR,
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.name = DRIVER_NAME,
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.fops = &axidma_fops,
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};
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static int __init axidma_init(void)
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{
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int ret = misc_register(&axidma_miscdev);
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if(ret) {
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printk (KERN_ERR "cannot register miscdev (err=%d)\n", ret);
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return ret;
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}
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memset(&channels, 0, sizeof(channels));
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return 0;
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}
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static void __exit axidma_exit(void)
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{
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misc_deregister(&axidma_miscdev);
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}
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module_init(axidma_init);
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module_exit(axidma_exit);
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MODULE_AUTHOR("samin.guo");
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MODULE_DESCRIPTION("DW Axi Dmac Driver");
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MODULE_LICENSE("GPL");
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288
drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
Normal file
288
drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c
Normal file
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@ -0,0 +1,288 @@
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/*
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* Copyright 2020 StarFive, Inc <samin.guo@starfivetech.com>
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*
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* API for dma mem2mem.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
|
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*/
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#include <linux/acpi_iort.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/cdev.h>
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#include <linux/dmaengine.h>
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#include <linux/wait.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-map-ops.h>
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#include <linux/slab.h>
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#include <soc/sifive/sifive_l2_cache.h>
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#include <soc/starfive/jh7100_dma.h>
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static volatile int dma_finished = 0;
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static DECLARE_WAIT_QUEUE_HEAD(wq);
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u64 dw_virt_to_phys(void *vaddr)
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{
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u64 pfn_offset = ((u64)vaddr) & 0xfff;
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return _dw_virt_to_phys((u64 *)vaddr) + pfn_offset;
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}
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EXPORT_SYMBOL(dw_virt_to_phys);
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void *dw_phys_to_virt(u64 phys)
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{
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u64 pfn_offset = phys & 0xfff;
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return (void *)(_dw_phys_to_virt(phys) + pfn_offset);
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}
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EXPORT_SYMBOL(dw_phys_to_virt);
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static void tx_callback(void *dma_async_param)
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{
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dma_finished = 1;
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wake_up_interruptible(&wq);
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}
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static int _dma_async_alloc_buf(struct device *dma_dev,
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void **src, void **dst, size_t size,
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dma_addr_t *src_dma, dma_addr_t *dst_dma)
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{
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*src = dma_alloc_coherent(dma_dev, size, src_dma, GFP_KERNEL);
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if(!(*src)) {
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DMA_DEBUG("src alloc err.\n");
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goto _FAILED_ALLOC_SRC;
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}
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*dst = dma_alloc_coherent(dma_dev, size, dst_dma, GFP_KERNEL);
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if(!(*dst)) {
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DMA_DEBUG("dst alloc err.\n");
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goto _FAILED_ALLOC_DST;
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}
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return 0;
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_FAILED_ALLOC_DST:
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dma_free_coherent(dma_dev, size, *src, *src_dma);
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_FAILED_ALLOC_SRC:
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dma_free_coherent(dma_dev, size, *dst, *dst_dma);
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return -1;
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}
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static int _dma_async_prebuf(void *src, void *dst, size_t size)
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{
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memset((u8 *)src, 0xff, size);
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memset((u8 *)dst, 0x00, size);
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return 0;
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}
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static int _dma_async_check_data(void *src, void *dst, size_t size)
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{
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return memcmp(src, dst, size);
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}
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static void _dma_async_release(struct dma_chan *chan)
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{
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dma_release_channel(chan);
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}
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|
||||
static struct dma_chan *_dma_get_channel(enum dma_transaction_type tx_type)
|
||||
{
|
||||
dma_cap_mask_t dma_mask;
|
||||
|
||||
dma_cap_zero(dma_mask);
|
||||
dma_cap_set(tx_type, dma_mask);
|
||||
|
||||
return dma_request_channel(dma_mask, NULL, NULL);
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *_dma_async_get_desc(
|
||||
struct dma_chan *chan,
|
||||
dma_addr_t src_dma, dma_addr_t dst_dma,
|
||||
size_t size)
|
||||
{
|
||||
dma_finished = 0;
|
||||
return dmaengine_prep_dma_memcpy(chan, dst_dma, src_dma, size,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
}
|
||||
|
||||
static void _dma_async_do_start(struct dma_async_tx_descriptor *desc,
|
||||
struct dma_chan *chan)
|
||||
{
|
||||
dma_cookie_t dma_cookie = dmaengine_submit(desc);
|
||||
if (dma_submit_error(dma_cookie))
|
||||
DMA_DEBUG("Failed to do DMA tx_submit\n");
|
||||
|
||||
dma_async_issue_pending(chan);
|
||||
wait_event_interruptible(wq, dma_finished);
|
||||
}
|
||||
|
||||
int dw_dma_async_do_memcpy(void *src, void *dst, size_t size)
|
||||
{
|
||||
int ret;
|
||||
struct device *dma_dev;
|
||||
struct dma_chan *chan;
|
||||
dma_addr_t src_dma, dst_dma;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
|
||||
const struct iommu_ops *iommu;
|
||||
u64 dma_addr = 0, dma_size = 0;
|
||||
|
||||
dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
|
||||
if(!dma_dev){
|
||||
dev_err(dma_dev, "kmalloc error.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_dev->bus = NULL;
|
||||
dma_dev->coherent_dma_mask = 0xffffffff;
|
||||
|
||||
iort_dma_setup(dma_dev, &dma_addr, &dma_size);
|
||||
iommu = iort_iommu_configure_id(dma_dev, NULL);
|
||||
if (PTR_ERR(iommu) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
|
||||
|
||||
if(_dma_async_alloc_buf(dma_dev, &src, &dst, size, &src_dma, &dst_dma)) {
|
||||
dev_err(dma_dev, "Err alloc.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
DMA_DEBUG("src=%#llx, dst=%#llx\n", (u64)src, (u64)dst);
|
||||
DMA_DEBUG("dma_src=%#x dma_dst=%#x\n", (u32)src_dma, (u32)dst_dma);
|
||||
|
||||
_dma_async_prebuf(src, dst, size);
|
||||
|
||||
chan = _dma_get_channel(DMA_MEMCPY);
|
||||
if(!chan ){
|
||||
DMA_PRINTK("Err get chan.\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
DMA_DEBUG("get chan ok.\n");
|
||||
|
||||
desc = _dma_async_get_desc(chan, src_dma, dst_dma, size);
|
||||
if(!desc){
|
||||
DMA_PRINTK("Err get desc.\n");
|
||||
dma_release_channel(chan);
|
||||
return -ENOMEM;
|
||||
}
|
||||
DMA_DEBUG("get desc ok.\n");
|
||||
|
||||
desc->callback = tx_callback;
|
||||
|
||||
sifive_l2_flush64_range(src_dma, size);
|
||||
sifive_l2_flush64_range(dst_dma, size);
|
||||
|
||||
_dma_async_do_start(desc, chan);
|
||||
_dma_async_release(chan);
|
||||
|
||||
ret = _dma_async_check_data(src, dst, size);
|
||||
|
||||
dma_free_coherent(dma_dev, size, src, src_dma);
|
||||
dma_free_coherent(dma_dev, size, dst, dst_dma);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_async_do_memcpy);
|
||||
|
||||
/*
|
||||
* phys addr for dma.
|
||||
*/
|
||||
int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size)
|
||||
{
|
||||
struct dma_chan *chan;
|
||||
struct device *dma_dev;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
|
||||
const struct iommu_ops *iommu;
|
||||
u64 dma_addr = 0, dma_size = 0;
|
||||
|
||||
dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
|
||||
if(!dma_dev){
|
||||
DMA_PRINTK("kmalloc error.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_dev->bus = NULL;
|
||||
dma_dev->coherent_dma_mask = 0xffffffff;
|
||||
|
||||
iort_dma_setup(dma_dev, &dma_addr, &dma_size);
|
||||
iommu = iort_iommu_configure_id(dma_dev, NULL);
|
||||
if (PTR_ERR(iommu) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
arch_setup_dma_ops(dma_dev, dst_dma, dma_size, iommu, true);
|
||||
|
||||
chan = _dma_get_channel(DMA_MEMCPY);
|
||||
if(!chan){
|
||||
DMA_PRINTK("Error get chan.\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
DMA_DEBUG("get chan ok.\n");
|
||||
|
||||
DMA_DEBUG("src_dma=%#llx, dst_dma=%#llx \n", src_dma, dst_dma);
|
||||
desc = _dma_async_get_desc(chan, src_dma, dst_dma, size);
|
||||
if(!desc){
|
||||
DMA_PRINTK("Error get desc.\n");
|
||||
dma_release_channel(chan);
|
||||
return -ENOMEM;
|
||||
}
|
||||
DMA_DEBUG("get desc ok.\n");
|
||||
|
||||
desc->callback = tx_callback;
|
||||
|
||||
sifive_l2_flush64_range(src_dma, size);
|
||||
sifive_l2_flush64_range(dst_dma, size);
|
||||
|
||||
_dma_async_do_start(desc, chan);
|
||||
_dma_async_release(chan);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_memcpy_raw);
|
||||
|
||||
/*
|
||||
*virtl addr for cpu.
|
||||
*/
|
||||
int dw_dma_memcpy(void *src, void *dst, size_t size)
|
||||
{
|
||||
dma_addr_t src_dma, dst_dma;
|
||||
|
||||
src_dma = dw_virt_to_phys(src);
|
||||
dst_dma = dw_virt_to_phys(dst);
|
||||
|
||||
dw_dma_memcpy_raw(src_dma, dst_dma, size);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_memcpy);
|
||||
|
||||
int dw_dma_mem2mem_test(void)
|
||||
{
|
||||
int ret;
|
||||
void *src = NULL;
|
||||
void *dst = NULL;
|
||||
size_t size = 256;
|
||||
|
||||
ret = dw_dma_async_do_memcpy(src, dst, size);
|
||||
if(ret){
|
||||
DMA_PRINTK("memcpy failed.\n");
|
||||
} else {
|
||||
DMA_PRINTK("memcpy ok.\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
31
include/soc/starfive/jh7100_dma.h
Normal file
31
include/soc/starfive/jh7100_dma.h
Normal file
|
@ -0,0 +1,31 @@
|
|||
#ifndef STARFIVE_JH7100_DMA_H
|
||||
#define STARFIVE_JH7100_DMA_H
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CONFIG_DW_DEBUG
|
||||
|
||||
#define DMA_PRINTK(fmt,...) \
|
||||
printk("[DW_DMA] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
|
||||
#ifdef CONFIG_DW_DEBUG
|
||||
#define DMA_DEBUG(fmt,...) \
|
||||
printk("[DW_DMA_DEBUG] %s():%d \n" fmt, __func__, __LINE__, ##__VA_ARGS__)
|
||||
#else
|
||||
#define DMA_BEBUG(fmt,...)
|
||||
#endif
|
||||
|
||||
#define _dw_virt_to_phys(vaddr) (pfn_to_phys(virt_to_pfn(vaddr)))
|
||||
#define _dw_phys_to_virt(paddr) (page_to_virt(phys_to_page(paddr)))
|
||||
|
||||
void *dw_phys_to_virt(u64 phys);
|
||||
u64 dw_virt_to_phys(void *vaddr);
|
||||
|
||||
int dw_dma_async_do_memcpy(void *src, void *dst, size_t size);
|
||||
int dw_dma_memcpy_raw(dma_addr_t src_dma, dma_addr_t dst_dma, size_t size);
|
||||
int dw_dma_memcpy(void *src, void *dst, size_t size);
|
||||
|
||||
int dw_dma_mem2mem_arry(void);
|
||||
int dw_dma_mem2mem_test(void);
|
||||
|
||||
#endif /* STARFIVE_JH7100_DMA_H */
|
Loading…
Add table
Reference in a new issue