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MIPS: Move headfiles to new location below arch/mips/include

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2008-09-16 19:48:51 +02:00
parent e8c7c48234
commit 384740dc49
463 changed files with 82 additions and 82 deletions
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86
arch/mips/include/asm/sgi/gio.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* gio.h: Definitions for SGI GIO bus
*
* Copyright (C) 2002 Ladislav Michl
*/
#ifndef _SGI_GIO_H
#define _SGI_GIO_H
/*
* GIO bus addresses
*
* The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
* three physical connectors, but only two slots, GFX and EXP0.
*
* There is 10MB of GIO address space for GIO64 slot devices
* slot# slot type address range size
* ----- --------- ----------------------- -----
* 0 GFX 0x1f000000 - 0x1f3fffff 4MB
* 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
* 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
*
* There are un-slotted devices, HPC, I/O and misc devices, which are grouped
* into the HPC address space.
* - MISC 0x1fb00000 - 0x1fbfffff 1MB
*
* Following space is reserved and unused
* - RESERVED 0x18000000 - 0x1effffff 112MB
*
* GIO bus IDs
*
* Each GIO bus device identifies itself to the system by answering a
* read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
* than 128 are 8 bits long, with the most significant 24 bits read from
* the slot undefined.
*
* 32-bit IDs are divided into
* bits 0:6 the product ID; ranges from 0x00 to 0x7F.
* bit 7 0=GIO Product ID is 8 bits wide
* 1=GIO Product ID is 32 bits wide.
* bits 8:15 manufacturer version for the product.
* bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
* bit 17 0=no ROM present
* 1=ROM present on this board AND next three words
* space define the ROM.
* bits 18:31 up to manufacturer.
*
* IDs above 0x50/0xd0 are of 3rd party boards.
*
* 8-bit IDs
* 0x01 XPI low cost FDDI
* 0x02 GTR TokenRing
* 0x04 Synchronous ISDN
* 0x05 ATM board [*]
* 0x06 Canon Interface
* 0x07 16 bit SCSI Card [*]
* 0x08 JPEG (Double Wide)
* 0x09 JPEG (Single Wide)
* 0x0a XPI mez. FDDI device 0
* 0x0b XPI mez. FDDI device 1
* 0x0c SMPTE 259M Video [*]
* 0x0d Babblefish Compression [*]
* 0x0e E-Plex 8-port Ethernet
* 0x30 Lyon Lamb IVAS
* 0xb8 GIO 100BaseTX Fast Ethernet (gfe)
*
* [*] Device provide 32-bit ID.
*
*/
#define GIO_ID(x) (x & 0x7f)
#define GIO_32BIT_ID 0x80
#define GIO_REV(x) ((x >> 8) & 0xff)
#define GIO_64BIT_IFACE 0x10000
#define GIO_ROM_PRESENT 0x20000
#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff)
#define GIO_SLOT_GFX_BASE 0x1f000000
#define GIO_SLOT_EXP0_BASE 0x1f400000
#define GIO_SLOT_EXP1_BASE 0x1f600000
#endif /* _SGI_GIO_H */

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arch/mips/include/asm/sgi/hpc3.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* hpc3.h: Definitions for SGI HPC3 controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1998 Ralf Baechle
*/
#ifndef _SGI_HPC3_H
#define _SGI_HPC3_H
#include <linux/types.h>
#include <asm/page.h>
/* An HPC DMA descriptor. */
struct hpc_dma_desc {
u32 pbuf; /* physical address of data buffer */
u32 cntinfo; /* counter and info bits */
#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
u32 pnext; /* paddr of next hpc_dma_desc if any */
};
/* The set of regs for each HPC3 PBUS DMA channel. */
struct hpc3_pbus_dmacregs {
volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 pbdma_ctrl; /* pbus dma channel control register has
* copletely different meaning for read
* compared with write */
/* read */
#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
/* write */
#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
u32 _unused1[0x1000/4 - 1]; /* padding */
};
/* The HPC3 SCSI registers, this does not include external ones. */
struct hpc3_scsiregs {
volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 bcd; /* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
volatile u32 ctrl; /* control register */
#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
volatile u32 gfptr; /* current GIO fifo ptr */
volatile u32 dfptr; /* current device fifo ptr */
volatile u32 dconfig; /* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
volatile u32 pconfig; /* PIO configuration register */
#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
u32 _unused1[0x1000/4 - 6]; /* padding */
};
/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
/* Receiver registers. */
volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 rx_ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 rx_bcd; /* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
volatile u32 rx_ctrl; /* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
volatile u32 rx_gfptr; /* current GIO fifo ptr */
volatile u32 rx_dfptr; /* current device fifo ptr */
u32 _unused1; /* padding */
volatile u32 reset; /* reset register */
#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
volatile u32 dconfig; /* DMA configuration register */
#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */
volatile u32 pconfig; /* PIO configuration register */
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
u32 _unused2[0x1000/4 - 8]; /* padding */
/* Transmitter registers. */
volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 tx_ndptr; /* next dma descriptor ptr */
u32 _unused3[0x1000/4 - 2]; /* padding */
volatile u32 tx_bcd; /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
volatile u32 tx_ctrl; /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
volatile u32 tx_gfptr; /* current GIO fifo ptr */
volatile u32 tx_dfptr; /* current device fifo ptr */
u32 _unused4[0x1000/4 - 4]; /* padding */
};
struct hpc3_regs {
/* First regs for the PBUS 8 dma channels. */
struct hpc3_pbus_dmacregs pbdma[8];
/* Now the HPC scsi registers, we get two scsi reg sets. */
struct hpc3_scsiregs scsi_chan0, scsi_chan1;
/* The SEEQ hpc3 ethernet dma/control registers. */
struct hpc3_ethregs ethregs;
/* Here are where the hpc3 fifo's can be directly accessed
* via PIO accesses. Under normal operation we never stick
* our grubby paws in here so it's just padding. */
u32 _unused0[0x18000/4];
/* HPC3 irq status regs. Due to a peculiar bug you need to
* look at two different register addresses to get at all of
* the status bits. The first reg can only reliably report
* bits 4:0 of the status, and the second reg can only
* reliably report bits 9:5 of the hpc3 irq status. I told
* you it was a peculiar bug. ;-)
*/
volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
volatile u32 gio_misc; /* GIO misc control bits. */
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
u32 eeprom; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
#define HPC3_EEPROM_DATO 0x08 /* Data out */
#define HPC3_EEPROM_DATI 0x10 /* Data in */
volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
volatile u32 bestat; /* Bus error interrupt status reg. */
#define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
#define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_BESTAT_PIDSHIFT 9
#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
u32 _unused1[0x14000/4 - 5]; /* padding */
/* Now direct PIO per-HPC3 peripheral access to external regs. */
volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
u32 _unused2[0x7c00/4];
volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
u32 _unused3[0x7c00/4];
volatile u32 eth_ext[320]; /* Ethernet external registers */
u32 _unused4[0x3b00/4];
/* Per-peripheral device external registers and DMA/PIO control. */
volatile u32 pbus_extregs[16][256];
volatile u32 pbus_dmacfg[8][128];
/* Cycles to spend in D3 for reads */
#define HPC3_DMACFG_D3R_MASK 0x00000001
#define HPC3_DMACFG_D3R_SHIFT 0
/* Cycles to spend in D4 for reads */
#define HPC3_DMACFG_D4R_MASK 0x0000001e
#define HPC3_DMACFG_D4R_SHIFT 1
/* Cycles to spend in D5 for reads */
#define HPC3_DMACFG_D5R_MASK 0x000001e0
#define HPC3_DMACFG_D5R_SHIFT 5
/* Cycles to spend in D3 for writes */
#define HPC3_DMACFG_D3W_MASK 0x00000200
#define HPC3_DMACFG_D3W_SHIFT 9
/* Cycles to spend in D4 for writes */
#define HPC3_DMACFG_D4W_MASK 0x00003c00
#define HPC3_DMACFG_D4W_SHIFT 10
/* Cycles to spend in D5 for writes */
#define HPC3_DMACFG_D5W_MASK 0x0003c000
#define HPC3_DMACFG_D5W_SHIFT 14
/* Enable 16-bit DMA access mode */
#define HPC3_DMACFG_DS16 0x00040000
/* Places halfwords on high 16 bits of bus */
#define HPC3_DMACFG_EVENHI 0x00080000
/* Make this device real time */
#define HPC3_DMACFG_RTIME 0x00200000
/* 5 bit burst count for DMA device */
#define HPC3_DMACFG_BURST_MASK 0x07c00000
#define HPC3_DMACFG_BURST_SHIFT 22
/* Use live pbus_dreq unsynchronized signal */
#define HPC3_DMACFG_DRQLIVE 0x08000000
volatile u32 pbus_piocfg[16][64];
/* Cycles to spend in P2 state for reads */
#define HPC3_PIOCFG_P2R_MASK 0x00001
#define HPC3_PIOCFG_P2R_SHIFT 0
/* Cycles to spend in P3 state for reads */
#define HPC3_PIOCFG_P3R_MASK 0x0001e
#define HPC3_PIOCFG_P3R_SHIFT 1
/* Cycles to spend in P4 state for reads */
#define HPC3_PIOCFG_P4R_MASK 0x001e0
#define HPC3_PIOCFG_P4R_SHIFT 5
/* Cycles to spend in P2 state for writes */
#define HPC3_PIOCFG_P2W_MASK 0x00200
#define HPC3_PIOCFG_P2W_SHIFT 9
/* Cycles to spend in P3 state for writes */
#define HPC3_PIOCFG_P3W_MASK 0x03c00
#define HPC3_PIOCFG_P3W_SHIFT 10
/* Cycles to spend in P4 state for writes */
#define HPC3_PIOCFG_P4W_MASK 0x3c000
#define HPC3_PIOCFG_P4W_SHIFT 14
/* Enable 16-bit PIO accesses */
#define HPC3_PIOCFG_DS16 0x40000
/* Place even address bits in bits <15:8> */
#define HPC3_PIOCFG_EVENHI 0x80000
/* PBUS PROM control regs. */
volatile u32 pbus_promwe; /* PROM write enable register */
#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
u32 _unused5[0x0800/4 - 1];
volatile u32 pbus_promswap; /* Chip select swap reg */
#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
u32 _unused6[0x0800/4 - 1];
volatile u32 pbus_gout; /* PROM general purpose output reg */
#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
u32 _unused7[0x1000/4 - 1];
volatile u32 rtcregs[14]; /* Dallas clock registers */
u32 _unused8[50];
volatile u32 bbram[8192-50-14]; /* Battery backed ram */
};
/*
* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an Indy.
*/
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */
#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */
extern void sgihpc_init(void);
#endif /* _SGI_HPC3_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ioc.h: Definitions for SGI I/O Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
* Copyright (C) 2001, 2003 Ladislav Michl
*/
#ifndef _SGI_IOC_H
#define _SGI_IOC_H
#include <linux/types.h>
#include <asm/sgi/pi1.h>
/*
* All registers are 8-bit wide alligned on 32-bit boundary. Bad things
* happen if you try word access them. You have been warned.
*/
struct sgioc_uart_regs {
u8 _ctrl1[3];
volatile u8 ctrl1;
u8 _data1[3];
volatile u8 data1;
u8 _ctrl2[3];
volatile u8 ctrl2;
u8 _data2[3];
volatile u8 data2;
};
struct sgioc_keyb_regs {
u8 _data[3];
volatile u8 data;
u8 _command[3];
volatile u8 command;
};
struct sgint_regs {
u8 _istat0[3];
volatile u8 istat0; /* Interrupt status zero */
#define SGINT_ISTAT0_FFULL 0x01
#define SGINT_ISTAT0_SCSI0 0x02
#define SGINT_ISTAT0_SCSI1 0x04
#define SGINT_ISTAT0_ENET 0x08
#define SGINT_ISTAT0_GFXDMA 0x10
#define SGINT_ISTAT0_PPORT 0x20
#define SGINT_ISTAT0_HPC2 0x40
#define SGINT_ISTAT0_LIO2 0x80
u8 _imask0[3];
volatile u8 imask0; /* Interrupt mask zero */
u8 _istat1[3];
volatile u8 istat1; /* Interrupt status one */
#define SGINT_ISTAT1_ISDNI 0x01
#define SGINT_ISTAT1_PWR 0x02
#define SGINT_ISTAT1_ISDNH 0x04
#define SGINT_ISTAT1_LIO3 0x08
#define SGINT_ISTAT1_HPC3 0x10
#define SGINT_ISTAT1_AFAIL 0x20
#define SGINT_ISTAT1_VIDEO 0x40
#define SGINT_ISTAT1_GIO2 0x80
u8 _imask1[3];
volatile u8 imask1; /* Interrupt mask one */
u8 _vmeistat[3];
volatile u8 vmeistat; /* VME interrupt status */
u8 _cmeimask0[3];
volatile u8 cmeimask0; /* VME interrupt mask zero */
u8 _cmeimask1[3];
volatile u8 cmeimask1; /* VME interrupt mask one */
u8 _cmepol[3];
volatile u8 cmepol; /* VME polarity */
u8 _tclear[3];
volatile u8 tclear;
u8 _errstat[3];
volatile u8 errstat; /* Error status reg, reserved on INT2 */
u32 _unused0[2];
u8 _tcnt0[3];
volatile u8 tcnt0; /* counter 0 */
u8 _tcnt1[3];
volatile u8 tcnt1; /* counter 1 */
u8 _tcnt2[3];
volatile u8 tcnt2; /* counter 2 */
u8 _tcword[3];
volatile u8 tcword; /* control word */
#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
};
/*
* The timer is the good old 8254. Unlike in PCs it's clocked at exactly 1MHz
*/
#define SGINT_TIMER_CLOCK 1000000
/*
* This is the constant we're using for calibrating the counter.
*/
#define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255)
/* We need software copies of these because they are write only. */
extern u8 sgi_ioc_reset, sgi_ioc_write;
struct sgioc_regs {
struct pi1_regs pport;
u32 _unused0[2];
struct sgioc_uart_regs uart;
struct sgioc_keyb_regs kbdmouse;
u8 _gcsel[3];
volatile u8 gcsel;
u8 _genctrl[3];
volatile u8 genctrl;
u8 _panel[3];
volatile u8 panel;
#define SGIOC_PANEL_POWERON 0x01
#define SGIOC_PANEL_POWERINTR 0x02
#define SGIOC_PANEL_VOLDNINTR 0x10
#define SGIOC_PANEL_VOLDNHOLD 0x20
#define SGIOC_PANEL_VOLUPINTR 0x40
#define SGIOC_PANEL_VOLUPHOLD 0x80
u32 _unused1;
u8 _sysid[3];
volatile u8 sysid;
#define SGIOC_SYSID_FULLHOUSE 0x01
#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
u32 _unused2;
u8 _read[3];
volatile u8 read;
u32 _unused3;
u8 _dmasel[3];
volatile u8 dmasel;
#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */
#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */
#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */
#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */
u32 _unused4;
u8 _reset[3];
volatile u8 reset;
#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */
#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */
#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */
#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */
#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */
#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */
u32 _unused5;
u8 _write[3];
volatile u8 write;
#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */
#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */
#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */
u32 _unused6;
struct sgint_regs int3;
u32 _unused7[16];
volatile u32 extio; /* FullHouse only */
#define EXTIO_S0_IRQ_3 0x8000 /* S0: vid.vsync */
#define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */
#define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */
#define EXTIO_S0_RETRACE 0x1000
#define EXTIO_SG_IRQ_3 0x0800 /* SG: vid.vsync */
#define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */
#define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */
#define EXTIO_SG_RETRACE 0x0100
#define EXTIO_GIO_33MHZ 0x0080
#define EXTIO_EISA_BUSERR 0x0040
#define EXTIO_MC_BUSERR 0x0020
#define EXTIO_HPC3_BUSERR 0x0010
#define EXTIO_S0_STAT_1 0x0008
#define EXTIO_S0_STAT_0 0x0004
#define EXTIO_SG_STAT_1 0x0002
#define EXTIO_SG_STAT_0 0x0001
};
extern struct sgioc_regs *sgioc;
extern struct sgint_regs *sgint;
#endif

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ip22.h: Definitions for SGI IP22 machines
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
*/
#ifndef _SGI_IP22_H
#define _SGI_IP22_H
/*
* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
* are not supported this way. Driver is supposed to allocate HPC/MC
* interrupt as shareable and then look to proper status bit (see
* HAL2 driver). This will prevent many complications, trust me ;-)
*/
#include <irq.h>
#include <asm/sgi/ioc.h>
#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
/*
* Individual interrupt definitions for the Indy and Indigo2
*/
#define SGI_SOFT_0_IRQ SGINT_CPU + 0
#define SGI_SOFT_1_IRQ SGINT_CPU + 1
#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
#define SGI_8254_0_IRQ SGINT_CPU + 4
#define SGI_8254_1_IRQ SGINT_CPU + 5
#define SGI_BUSERR_IRQ SGINT_CPU + 6
#define SGI_TIMER_IRQ SGINT_CPU + 7
#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg);
#endif

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* mc.h: Definitions for SGI Memory Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _SGI_MC_H
#define _SGI_MC_H
struct sgimc_regs {
u32 _unused0;
volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
u32 _unused1;
volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
u32 _unused2;
volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
u32 _unused3;
volatile u32 systemid; /* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
u32 _unused4[3];
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused5;
u32 eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
u32 _unused6[3];
volatile u32 rcntpre; /* Preload refresh counter */
u32 _unused7;
volatile u32 rcounter; /* Readonly refresh counter */
u32 _unused8[13];
volatile u32 giopar; /* Parameter word for GIO64 */
#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
u32 _unused9;
volatile u32 cputp; /* CPU bus arb time period */
u32 _unused10[3];
volatile u32 lbursttp; /* Time period for long bursts */
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
* be the same size. The size encoding for supported SIMMs is bellow */
u32 _unused11[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused12;
volatile u32 mconfig1; /* Memory config register one */
#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/
#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */
#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */
u32 _unused13;
volatile u32 cmacc; /* Mem access config for CPU */
u32 _unused14;
volatile u32 gmacc; /* Mem access config for GIO */
/* This define applies to both cmacc and gmacc registers above. */
#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
/* Error address/status regs from GIO and CPU perspectives. */
u32 _unused15;
volatile u32 cerr; /* Error address reg for CPU */
u32 _unused16;
volatile u32 cstat; /* Status reg for CPU */
#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */
#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */
#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */
#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */
#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */
#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */
#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
u32 _unused17;
volatile u32 gerr; /* Error address reg for GIO */
u32 _unused18;
volatile u32 gstat; /* Status reg for GIO */
#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */
#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */
#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */
#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */
#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */
#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */
#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */
/* Special hard bus locking registers. */
u32 _unused19;
volatile u32 syssembit; /* Uni-bit system semaphore */
u32 _unused20;
volatile u32 mlock; /* Global GIO memory access lock */
u32 _unused21;
volatile u32 elock; /* Locks EISA from GIO accesses */
/* GIO dma control registers. */
u32 _unused22[15];
volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
u32 _unused23;
volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
u32 _unused24;
volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
u32 _unused25;
volatile u32 dma_ctrl; /* Main DMA control reg */
/* DMA TLB entry 0 */
u32 _unused26[5];
volatile u32 dtlb_hi0;
u32 _unused27;
volatile u32 dtlb_lo0;
/* DMA TLB entry 1 */
u32 _unused28;
volatile u32 dtlb_hi1;
u32 _unused29;
volatile u32 dtlb_lo1;
/* DMA TLB entry 2 */
u32 _unused30;
volatile u32 dtlb_hi2;
u32 _unused31;
volatile u32 dtlb_lo2;
/* DMA TLB entry 3 */
u32 _unused32;
volatile u32 dtlb_hi3;
u32 _unused33;
volatile u32 dtlb_lo3;
u32 _unused34[0x0392];
u32 _unused35;
volatile u32 rpsscounter; /* Chirps at 100ns */
u32 _unused36[0x1000/4-2*4];
u32 _unused37;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused38;
volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
u32 _unused39;
volatile u32 dmasz; /* DMA count */
u32 _unused40;
volatile u32 ssize; /* DMA stride size */
u32 _unused41;
volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */
u32 _unused42;
volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
u32 _unused43;
volatile u32 dmamode; /* DMA mode config bit settings */
u32 _unused44;
volatile u32 dmaccount; /* Zoom and byte count for DMA */
u32 _unused45;
volatile u32 dmastart; /* Pedal to the metal. */
u32 _unused46;
volatile u32 dmarunning; /* DMA op is in progress */
u32 _unused47;
volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */
};
extern struct sgimc_regs *sgimc;
#define SGIMC_BASE 0x1fa00000 /* physical */
/* Base location of the two ram banks found in IP2[0268] machines. */
#define SGIMC_SEG0_BADDR 0x08000000
#define SGIMC_SEG1_BADDR 0x20000000
/* Maximum size of the above banks are per machine. */
#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
extern void sgimc_init(void);
#endif /* _SGI_MC_H */

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/*
* pi1.h: Definitions for SGI PI1 parallel port
*/
#ifndef _SGI_PI1_H
#define _SGI_PI1_H
struct pi1_regs {
u8 _data[3];
volatile u8 data;
u8 _ctrl[3];
volatile u8 ctrl;
#define PI1_CTRL_STROBE_N 0x01
#define PI1_CTRL_AFD_N 0x02
#define PI1_CTRL_INIT_N 0x04
#define PI1_CTRL_SLIN_N 0x08
#define PI1_CTRL_IRQ_ENA 0x10
#define PI1_CTRL_DIR 0x20
#define PI1_CTRL_SEL 0x40
u8 _status[3];
volatile u8 status;
#define PI1_STAT_DEVID 0x03 /* bits 0-1 */
#define PI1_STAT_NOINK 0x04 /* SGI MODE only */
#define PI1_STAT_ERROR 0x08
#define PI1_STAT_ONLINE 0x10
#define PI1_STAT_PE 0x20
#define PI1_STAT_ACK 0x40
#define PI1_STAT_BUSY 0x80
u8 _dmactrl[3];
volatile u8 dmactrl;
#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */
#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */
#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */
#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */
#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */
#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */
#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */
#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */
#define PI1_DMACTRL_READ 0x40 /* read */
#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */
u8 _intstat[3];
volatile u8 intstat;
#define PI1_INTSTAT_ACK 0x04
#define PI1_INTSTAT_FEMPTY 0x08
#define PI1_INTSTAT_NOINK 0x10
#define PI1_INTSTAT_ONLINE 0x20
#define PI1_INTSTAT_ERR 0x40
#define PI1_INTSTAT_PE 0x80
u8 _intmask[3];
volatile u8 intmask; /* enabled low, reset high*/
#define PI1_INTMASK_ACK 0x04
#define PI1_INTMASK_FIFO_EMPTY 0x08
#define PI1_INTMASK_NOINK 0x10
#define PI1_INTMASK_ONLINE 0x20
#define PI1_INTMASK_ERR 0x40
#define PI1_INTMASK_PE 0x80
u8 _timer1[3];
volatile u8 timer1;
#define PI1_TIME1 0x27
u8 _timer2[3];
volatile u8 timer2;
#define PI1_TIME2 0x13
u8 _timer3[3];
volatile u8 timer3;
#define PI1_TIME3 0x10
u8 _timer4[3];
volatile u8 timer4;
#define PI1_TIME4 0x00
};
#endif

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 by Ralf Baechle
*/
#ifndef __ASM_SGI_SEEQ_H
#define __ASM_SGI_SEEQ_H
#include <linux/if_ether.h>
#include <asm/sgi/hpc3.h>
struct sgiseeq_platform_data {
struct hpc3_regs *hpc;
unsigned int irq;
unsigned char mac[ETH_ALEN];
};
#endif /* __ASM_SGI_SEEQ_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgi.h: Definitions specific to SGI machines.
*
* Copyright (C) 1996 David S. Miller (dm@sgi.com)
*/
#ifndef _ASM_SGI_SGI_H
#define _ASM_SGI_SGI_H
/* UP=UniProcessor MP=MultiProcessor(capable) */
enum sgi_mach {
ip4, /* R2k UP */
ip5, /* R2k MP */
ip6, /* R3k UP */
ip7, /* R3k MP */
ip9, /* R3k UP */
ip12, /* R3kA UP, Indigo */
ip15, /* R3kA MP */
ip17, /* R4K UP */
ip19, /* R4K MP */
ip20, /* R4K UP, Indigo */
ip21, /* TFP MP */
ip22, /* R4x00 UP, Indigo2 */
ip25, /* R10k MP */
ip26, /* TFP UP, Indigo2 */
ip27, /* R10k MP, R12k MP, Origin */
ip28, /* R10k UP, Indigo2 */
ip30, /* Octane */
ip32, /* O2 */
};
extern enum sgi_mach sgimach;
extern void sgi_sysinit(void);
/* Many I/O space registers are byte sized and are contained within
* one byte per word, specifically the MSB, this macro helps out.
*/
#ifdef __MIPSEL__
#define SGI_MSB(regaddr) (regaddr)
#else
#define SGI_MSB(regaddr) ((regaddr) | 0x3)
#endif
#endif /* _ASM_SGI_SGI_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 by Ralf Baechle
*/
#ifndef __ASM_SGI_WD_H
#define __ASM_SGI_WD_H
#include <asm/sgi/hpc3.h>
struct sgiwd93_platform_data {
unsigned int unit;
unsigned int irq;
struct hpc3_scsiregs *hregs;
unsigned char *wdregs;
};
#endif /* __ASM_SGI_WD_H */