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mtd: rawnand: cadence: get meta data size from registers

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Add checking size of BCH meta data size in capabilities registers
instead of using fixed value. BCH meta data is used to keep data
from NAND flash OOB area.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1581328530-29966-1-git-send-email-piotrs@cadence.com
This commit is contained in:
Piotr Sroka 2020-02-10 10:55:25 +01:00 • committed by Miquel Raynal
parent 03a539c7a1
commit 397deafc02
1 changed files with 14 additions and 7 deletions
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21
drivers/mtd/nand/raw/cadence-nand-controller.c
View file

@ -30,7 +30,6 @@
* Generic mode is used for executing rest of commands.
*/
#define MAX_OOB_SIZE_PER_SECTOR 32
#define MAX_ADDRESS_CYC 6
#define MAX_ERASE_ADDRESS_CYC 3
#define MAX_DATA_SIZE 0xFFFC
@ -190,6 +189,7 @@
/* BCH Engine identification register 3. */
#define BCH_CFG_3 0x844
#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
/* Ready/Busy# line status. */
#define RBN_SETINGS 0x1004
@ -499,6 +499,7 @@ struct cdns_nand_ctrl {
unsigned long assigned_cs;
struct list_head chips;
u8 bch_metadata_size;
};
struct cdns_nand_chip {
@ -1077,6 +1078,14 @@ static int cadence_nand_read_bch_caps(struct cdns_nand_ctrl *cdns_ctrl)
int max_step_size = 0, nstrengths, i;
u32 reg;
reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3);
cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
if (cdns_ctrl->bch_metadata_size < 4) {
dev_err(cdns_ctrl->dev,
"Driver needs at least 4 bytes of BCH meta data\n");
return -EIO;
}
reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0);
cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
@ -1170,7 +1179,8 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)
writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS);
cadence_nand_get_caps(cdns_ctrl);
cadence_nand_read_bch_caps(cdns_ctrl);
if (cadence_nand_read_bch_caps(cdns_ctrl))
return -EIO;
/*
* Set IO width access to 8.
@ -2587,7 +2597,6 @@ int cadence_nand_attach_chip(struct nand_chip *chip)
struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
u32 ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
struct mtd_info *mtd = nand_to_mtd(chip);
u32 max_oob_data_size;
int ret;
if (chip->options & NAND_BUSWIDTH_16) {
@ -2628,10 +2637,8 @@ int cadence_nand_attach_chip(struct nand_chip *chip)
cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
max_oob_data_size = MAX_OOB_SIZE_PER_SECTOR;
if (cdns_chip->avail_oob_size > max_oob_data_size)
cdns_chip->avail_oob_size = max_oob_data_size;
if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size)
cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size;
if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
> mtd->oobsize)