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pci-v4.18-changes
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Merge tag 'pci-v4.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- unify AER decoding for native and ACPI CPER sources (Alexandru
Gagniuc)
- add TLP header info to AER tracepoint (Thomas Tai)
- add generic pcie_wait_for_link() interface (Oza Pawandeep)
- handle AER ERR_FATAL by removing and re-enumerating devices, as
Downstream Port Containment does (Oza Pawandeep)
- factor out common code between AER and DPC recovery (Oza Pawandeep)
- stop triggering DPC for ERR_NONFATAL errors (Oza Pawandeep)
- share ERR_FATAL recovery path between AER and DPC (Oza Pawandeep)
- disable ASPM L1.2 substate if we don't have LTR (Bjorn Helgaas)
- respect platform ownership of LTR (Bjorn Helgaas)
- clear interrupt status in top half to avoid interrupt storm (Oza
Pawandeep)
- neaten pci=earlydump output (Andy Shevchenko)
- avoid errors when extended config space inaccessible (Gilles Buloz)
- prevent sysfs disable of device while driver attached (Christoph
Hellwig)
- use core interface to report PCIe link properties in bnx2x, bnxt_en,
cxgb4, ixgbe (Bjorn Helgaas)
- remove unused pcie_get_minimum_link() (Bjorn Helgaas)
- fix use-before-set error in ibmphp (Dan Carpenter)
- fix pciehp timeouts caused by Command Completed errata (Bjorn
Helgaas)
- fix refcounting in pnv_php hotplug (Julia Lawall)
- clear pciehp Presence Detect and Data Link Layer Status Changed on
resume so we don't miss hotplug events (Mika Westerberg)
- only request pciehp control if we support it, so platform can use
ACPI hotplug otherwise (Mika Westerberg)
- convert SHPC to be builtin only (Mika Westerberg)
- request SHPC control via _OSC if we support it (Mika Westerberg)
- simplify SHPC handoff from firmware (Mika Westerberg)
- fix an SHPC quirk that mistakenly included *all* AMD bridges as well
as devices from any vendor with device ID 0x7458 (Bjorn Helgaas)
- assign a bus number even to non-native hotplug bridges to leave
space for acpiphp additions, to fix a common Thunderbolt xHCI
hot-add failure (Mika Westerberg)
- keep acpiphp from scanning native hotplug bridges, to fix common
Thunderbolt hot-add failures (Mika Westerberg)
- improve "partially hidden behind bridge" messages from core (Mika
Westerberg)
- add macros for PCIe Link Control 2 register (Frederick Lawler)
- replace IB/hfi1 custom macros with PCI core versions (Frederick
Lawler)
- remove dead microblaze and xtensa code (Bjorn Helgaas)
- use dev_printk() when possible in xtensa and mips (Bjorn Helgaas)
- remove unused pcie_port_acpi_setup() and portdrv_acpi.c (Bjorn
Helgaas)
- add managed interface to get PCI host bridge resources from OF (Jan
Kiszka)
- add support for unbinding generic PCI host controller (Jan Kiszka)
- fix memory leaks when unbinding generic PCI host controller (Jan
Kiszka)
- request legacy VGA framebuffer only for VGA devices to avoid false
device conflicts (Bjorn Helgaas)
- turn on PCI_COMMAND_IO & PCI_COMMAND_MEMORY in pci_enable_device()
like everybody else, not in pcibios_fixup_bus() (Bjorn Helgaas)
- add generic enable function for simple SR-IOV hardware (Alexander
Duyck)
- use generic SR-IOV enable for ena, nvme (Alexander Duyck)
- add ACS quirk for Intel 7th & 8th Gen mobile (Alex Williamson)
- add ACS quirk for Intel 300 series (Mika Westerberg)
- enable register clock for Armada 7K/8K (Gregory CLEMENT)
- reduce Keystone "link already up" log level (Fabio Estevam)
- move private DT functions to drivers/pci/ (Rob Herring)
- factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring)
- add DesignWare support to the endpoint test driver (Gustavo
Pimentel)
- add DesignWare support for endpoint mode (Gustavo Pimentel)
- use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and
artpec6 (Gustavo Pimentel)
- fix Qualcomm bitwise NOT issue (Dan Carpenter)
- add Qualcomm runtime PM support (Srinivas Kandagatla)
- fix DesignWare enumeration below bridges (Koen Vandeputte)
- use usleep() instead of mdelay() in endpoint test (Jia-Ju Bai)
- add configfs entries for pci_epf_driver device IDs (Kishon Vijay
Abraham I)
- clean up pci_endpoint_test driver (Gustavo Pimentel)
- update Layerscape maintainer email addresses (Minghuan Lian)
- add COMPILE_TEST to improve build test coverage (Rob Herring)
- fix Hyper-V bus registration failure caused by domain/serial number
confusion (Sridhar Pitchai)
- improve Hyper-V refcounting and coding style (Stephen Hemminger)
- avoid potential Hyper-V hang waiting for a response that will never
come (Dexuan Cui)
- implement Mediatek chained IRQ handling (Honghui Zhang)
- fix vendor ID & class type for Mediatek MT7622 (Honghui Zhang)
- add Mobiveil PCIe host controller driver (Subrahmanya Lingappa)
- add Mobiveil MSI support (Subrahmanya Lingappa)
- clean up clocks, MSI, IRQ mappings in R-Car probe failure paths
(Marek Vasut)
- poll more frequently (5us vs 5ms) while waiting for R-Car data link
active (Marek Vasut)
- use generic OF parsing interface in R-Car (Vladimir Zapolskiy)
- add R-Car V3H (R8A77980) "compatible" string (Sergei Shtylyov)
- add R-Car gen3 PHY support (Sergei Shtylyov)
- improve R-Car PHYRDY polling (Sergei Shtylyov)
- clean up R-Car macros (Marek Vasut)
- use runtime PM for R-Car controller clock (Dien Pham)
- update arm64 defconfig for Rockchip (Shawn Lin)
- refactor Rockchip code to facilitate both root port and endpoint
mode (Shawn Lin)
- add Rockchip endpoint mode driver (Shawn Lin)
- support VMD "membar shadow" feature (Jon Derrick)
- support VMD bus number offsets (Jon Derrick)
- add VMD "no AER source ID" quirk for more device IDs (Jon Derrick)
- remove unnecessary host controller CONFIG_PCIEPORTBUS Kconfig
selections (Bjorn Helgaas)
- clean up quirks.c organization and whitespace (Bjorn Helgaas)
* tag 'pci-v4.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (144 commits)
PCI/AER: Replace struct pcie_device with pci_dev
PCI/AER: Remove unused parameters
PCI: qcom: Include gpio/consumer.h
PCI: Improve "partially hidden behind bridge" log message
PCI: Improve pci_scan_bridge() and pci_scan_bridge_extend() doc
PCI: Move resource distribution for single bridge outside loop
PCI: Account for all bridges on bus when distributing bus numbers
ACPI / hotplug / PCI: Drop unnecessary parentheses
ACPI / hotplug / PCI: Mark stale PCI devices disconnected
ACPI / hotplug / PCI: Don't scan bridges managed by native hotplug
PCI: hotplug: Add hotplug_is_native()
PCI: shpchp: Add shpchp_is_native()
PCI: shpchp: Fix AMD POGO identification
PCI: mobiveil: Add MSI support
PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver
PCI/AER: Decode Error Source Requester ID
PCI/AER: Remove aer_recover_work_func() forward declaration
PCI/DPC: Use the generic pcie_do_fatal_recovery() path
PCI/AER: Pass service type to pcie_do_fatal_recovery()
PCI/DPC: Disable ERR_NONFATAL handling by DPC
...
This commit is contained in:
Linus Torvalds
commit
3a3869f1c4
120 changed files with 6189 additions and 3863 deletions
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@ -112,6 +112,14 @@ unsigned int pcibios_max_latency = 255;
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/* If set, the PCIe ARI capability will not be used. */
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static bool pcie_ari_disabled;
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/* If set, the PCIe ATS capability will not be used. */
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static bool pcie_ats_disabled;
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bool pci_ats_disabled(void)
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{
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return pcie_ats_disabled;
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}
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/* Disable bridge_d3 for all PCIe ports */
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static bool pci_bridge_d3_disable;
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/* Force bridge_d3 for all PCIe ports */
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@ -4153,6 +4161,35 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
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return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
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}
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/**
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* pcie_wait_for_link - Wait until link is active or inactive
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* @pdev: Bridge device
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* @active: waiting for active or inactive?
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*
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* Use this to wait till link becomes active or inactive.
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*/
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bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
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{
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int timeout = 1000;
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bool ret;
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u16 lnk_status;
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for (;;) {
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
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if (ret == active)
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return true;
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if (timeout <= 0)
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break;
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msleep(10);
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timeout -= 10;
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}
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pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
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active ? "set" : "cleared");
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return false;
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}
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void pci_reset_secondary_bus(struct pci_dev *dev)
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{
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@ -5084,49 +5121,6 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
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}
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EXPORT_SYMBOL(pcie_set_mps);
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/**
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* pcie_get_minimum_link - determine minimum link settings of a PCI device
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* @dev: PCI device to query
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* @speed: storage for minimum speed
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* @width: storage for minimum width
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*
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* This function will walk up the PCI device chain and determine the minimum
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* link width and speed of the device.
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*/
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int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width)
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{
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int ret;
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*speed = PCI_SPEED_UNKNOWN;
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*width = PCIE_LNK_WIDTH_UNKNOWN;
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while (dev) {
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u16 lnksta;
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enum pci_bus_speed next_speed;
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enum pcie_link_width next_width;
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ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
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if (ret)
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return ret;
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next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
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next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
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PCI_EXP_LNKSTA_NLW_SHIFT;
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if (next_speed < *speed)
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*speed = next_speed;
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if (next_width < *width)
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*width = next_width;
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dev = dev->bus->self;
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}
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return 0;
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}
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EXPORT_SYMBOL(pcie_get_minimum_link);
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/**
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* pcie_bandwidth_available - determine minimum link settings of a PCIe
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* device and its bandwidth limitation
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@ -5717,15 +5711,14 @@ static void pci_no_domains(void)
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#endif
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}
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#ifdef CONFIG_PCI_DOMAINS
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#ifdef CONFIG_PCI_DOMAINS_GENERIC
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static atomic_t __domain_nr = ATOMIC_INIT(-1);
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int pci_get_new_domain_nr(void)
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static int pci_get_new_domain_nr(void)
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{
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return atomic_inc_return(&__domain_nr);
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}
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#ifdef CONFIG_PCI_DOMAINS_GENERIC
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static int of_pci_bus_find_domain_nr(struct device *parent)
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{
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static int use_dt_domains = -1;
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@ -5780,7 +5773,6 @@ int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
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acpi_pci_bus_find_domain_nr(bus);
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}
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#endif
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#endif
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/**
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* pci_ext_cfg_avail - can we access extended PCI config space?
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@ -5808,6 +5800,9 @@ static int __init pci_setup(char *str)
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if (*str && (str = pcibios_setup(str)) && *str) {
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if (!strcmp(str, "nomsi")) {
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pci_no_msi();
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} else if (!strncmp(str, "noats", 5)) {
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pr_info("PCIe: ATS is disabled\n");
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pcie_ats_disabled = true;
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} else if (!strcmp(str, "noaer")) {
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pci_no_aer();
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} else if (!strncmp(str, "realloc=", 8)) {
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