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pci-v4.18-changes
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Merge tag 'pci-v4.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- unify AER decoding for native and ACPI CPER sources (Alexandru
Gagniuc)
- add TLP header info to AER tracepoint (Thomas Tai)
- add generic pcie_wait_for_link() interface (Oza Pawandeep)
- handle AER ERR_FATAL by removing and re-enumerating devices, as
Downstream Port Containment does (Oza Pawandeep)
- factor out common code between AER and DPC recovery (Oza Pawandeep)
- stop triggering DPC for ERR_NONFATAL errors (Oza Pawandeep)
- share ERR_FATAL recovery path between AER and DPC (Oza Pawandeep)
- disable ASPM L1.2 substate if we don't have LTR (Bjorn Helgaas)
- respect platform ownership of LTR (Bjorn Helgaas)
- clear interrupt status in top half to avoid interrupt storm (Oza
Pawandeep)
- neaten pci=earlydump output (Andy Shevchenko)
- avoid errors when extended config space inaccessible (Gilles Buloz)
- prevent sysfs disable of device while driver attached (Christoph
Hellwig)
- use core interface to report PCIe link properties in bnx2x, bnxt_en,
cxgb4, ixgbe (Bjorn Helgaas)
- remove unused pcie_get_minimum_link() (Bjorn Helgaas)
- fix use-before-set error in ibmphp (Dan Carpenter)
- fix pciehp timeouts caused by Command Completed errata (Bjorn
Helgaas)
- fix refcounting in pnv_php hotplug (Julia Lawall)
- clear pciehp Presence Detect and Data Link Layer Status Changed on
resume so we don't miss hotplug events (Mika Westerberg)
- only request pciehp control if we support it, so platform can use
ACPI hotplug otherwise (Mika Westerberg)
- convert SHPC to be builtin only (Mika Westerberg)
- request SHPC control via _OSC if we support it (Mika Westerberg)
- simplify SHPC handoff from firmware (Mika Westerberg)
- fix an SHPC quirk that mistakenly included *all* AMD bridges as well
as devices from any vendor with device ID 0x7458 (Bjorn Helgaas)
- assign a bus number even to non-native hotplug bridges to leave
space for acpiphp additions, to fix a common Thunderbolt xHCI
hot-add failure (Mika Westerberg)
- keep acpiphp from scanning native hotplug bridges, to fix common
Thunderbolt hot-add failures (Mika Westerberg)
- improve "partially hidden behind bridge" messages from core (Mika
Westerberg)
- add macros for PCIe Link Control 2 register (Frederick Lawler)
- replace IB/hfi1 custom macros with PCI core versions (Frederick
Lawler)
- remove dead microblaze and xtensa code (Bjorn Helgaas)
- use dev_printk() when possible in xtensa and mips (Bjorn Helgaas)
- remove unused pcie_port_acpi_setup() and portdrv_acpi.c (Bjorn
Helgaas)
- add managed interface to get PCI host bridge resources from OF (Jan
Kiszka)
- add support for unbinding generic PCI host controller (Jan Kiszka)
- fix memory leaks when unbinding generic PCI host controller (Jan
Kiszka)
- request legacy VGA framebuffer only for VGA devices to avoid false
device conflicts (Bjorn Helgaas)
- turn on PCI_COMMAND_IO & PCI_COMMAND_MEMORY in pci_enable_device()
like everybody else, not in pcibios_fixup_bus() (Bjorn Helgaas)
- add generic enable function for simple SR-IOV hardware (Alexander
Duyck)
- use generic SR-IOV enable for ena, nvme (Alexander Duyck)
- add ACS quirk for Intel 7th & 8th Gen mobile (Alex Williamson)
- add ACS quirk for Intel 300 series (Mika Westerberg)
- enable register clock for Armada 7K/8K (Gregory CLEMENT)
- reduce Keystone "link already up" log level (Fabio Estevam)
- move private DT functions to drivers/pci/ (Rob Herring)
- factor out dwc CONFIG_PCI Kconfig dependencies (Rob Herring)
- add DesignWare support to the endpoint test driver (Gustavo
Pimentel)
- add DesignWare support for endpoint mode (Gustavo Pimentel)
- use devm_ioremap_resource() instead of devm_ioremap() in dra7xx and
artpec6 (Gustavo Pimentel)
- fix Qualcomm bitwise NOT issue (Dan Carpenter)
- add Qualcomm runtime PM support (Srinivas Kandagatla)
- fix DesignWare enumeration below bridges (Koen Vandeputte)
- use usleep() instead of mdelay() in endpoint test (Jia-Ju Bai)
- add configfs entries for pci_epf_driver device IDs (Kishon Vijay
Abraham I)
- clean up pci_endpoint_test driver (Gustavo Pimentel)
- update Layerscape maintainer email addresses (Minghuan Lian)
- add COMPILE_TEST to improve build test coverage (Rob Herring)
- fix Hyper-V bus registration failure caused by domain/serial number
confusion (Sridhar Pitchai)
- improve Hyper-V refcounting and coding style (Stephen Hemminger)
- avoid potential Hyper-V hang waiting for a response that will never
come (Dexuan Cui)
- implement Mediatek chained IRQ handling (Honghui Zhang)
- fix vendor ID & class type for Mediatek MT7622 (Honghui Zhang)
- add Mobiveil PCIe host controller driver (Subrahmanya Lingappa)
- add Mobiveil MSI support (Subrahmanya Lingappa)
- clean up clocks, MSI, IRQ mappings in R-Car probe failure paths
(Marek Vasut)
- poll more frequently (5us vs 5ms) while waiting for R-Car data link
active (Marek Vasut)
- use generic OF parsing interface in R-Car (Vladimir Zapolskiy)
- add R-Car V3H (R8A77980) "compatible" string (Sergei Shtylyov)
- add R-Car gen3 PHY support (Sergei Shtylyov)
- improve R-Car PHYRDY polling (Sergei Shtylyov)
- clean up R-Car macros (Marek Vasut)
- use runtime PM for R-Car controller clock (Dien Pham)
- update arm64 defconfig for Rockchip (Shawn Lin)
- refactor Rockchip code to facilitate both root port and endpoint
mode (Shawn Lin)
- add Rockchip endpoint mode driver (Shawn Lin)
- support VMD "membar shadow" feature (Jon Derrick)
- support VMD bus number offsets (Jon Derrick)
- add VMD "no AER source ID" quirk for more device IDs (Jon Derrick)
- remove unnecessary host controller CONFIG_PCIEPORTBUS Kconfig
selections (Bjorn Helgaas)
- clean up quirks.c organization and whitespace (Bjorn Helgaas)
* tag 'pci-v4.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (144 commits)
PCI/AER: Replace struct pcie_device with pci_dev
PCI/AER: Remove unused parameters
PCI: qcom: Include gpio/consumer.h
PCI: Improve "partially hidden behind bridge" log message
PCI: Improve pci_scan_bridge() and pci_scan_bridge_extend() doc
PCI: Move resource distribution for single bridge outside loop
PCI: Account for all bridges on bus when distributing bus numbers
ACPI / hotplug / PCI: Drop unnecessary parentheses
ACPI / hotplug / PCI: Mark stale PCI devices disconnected
ACPI / hotplug / PCI: Don't scan bridges managed by native hotplug
PCI: hotplug: Add hotplug_is_native()
PCI: shpchp: Add shpchp_is_native()
PCI: shpchp: Fix AMD POGO identification
PCI: mobiveil: Add MSI support
PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver
PCI/AER: Decode Error Source Requester ID
PCI/AER: Remove aer_recover_work_func() forward declaration
PCI/DPC: Use the generic pcie_do_fatal_recovery() path
PCI/AER: Pass service type to pcie_do_fatal_recovery()
PCI/DPC: Disable ERR_NONFATAL handling by DPC
...
This commit is contained in:
Linus Torvalds
commit
3a3869f1c4
120 changed files with 6189 additions and 3863 deletions
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@ -217,6 +217,7 @@ enum pci_bus_flags {
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PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
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PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
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PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
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PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
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};
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/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
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@ -406,6 +407,9 @@ struct pci_dev {
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struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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#ifdef CONFIG_HOTPLUG_PCI_PCIE
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unsigned int broken_cmd_compl:1; /* No compl for some cmds */
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#endif
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#ifdef CONFIG_PCIE_PTM
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unsigned int ptm_root:1;
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unsigned int ptm_enabled:1;
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@ -471,8 +475,10 @@ struct pci_host_bridge {
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unsigned int ignore_reset_delay:1; /* For entire hierarchy */
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unsigned int no_ext_tags:1; /* No Extended Tags */
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unsigned int native_aer:1; /* OS may use PCIe AER */
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unsigned int native_hotplug:1; /* OS may use PCIe hotplug */
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unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
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unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
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unsigned int native_pme:1; /* OS may use PCIe PME */
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unsigned int native_ltr:1; /* OS may use PCIe LTR */
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/* Resource alignment requirements */
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resource_size_t (*align_resource)(struct pci_dev *dev,
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const struct resource *res,
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@ -1079,8 +1085,6 @@ int pcie_get_readrq(struct pci_dev *dev);
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int pcie_set_readrq(struct pci_dev *dev, int rq);
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int pcie_get_mps(struct pci_dev *dev);
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int pcie_set_mps(struct pci_dev *dev, int mps);
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int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
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enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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@ -1451,8 +1455,10 @@ static inline int pci_irqd_intx_xlate(struct irq_domain *d,
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#ifdef CONFIG_PCIEPORTBUS
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extern bool pcie_ports_disabled;
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extern bool pcie_ports_native;
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#else
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#define pcie_ports_disabled true
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#define pcie_ports_native false
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#endif
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#ifdef CONFIG_PCIEASPM
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@ -1479,6 +1485,8 @@ static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
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static inline void pcie_ecrc_get_policy(char *str) { }
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#endif
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bool pci_ats_disabled(void);
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#ifdef CONFIG_PCI_ATS
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/* Address Translation Service */
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void pci_ats_init(struct pci_dev *dev);
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@ -1510,12 +1518,10 @@ void pci_cfg_access_unlock(struct pci_dev *dev);
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*/
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#ifdef CONFIG_PCI_DOMAINS
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extern int pci_domains_supported;
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int pci_get_new_domain_nr(void);
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#else
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enum { pci_domains_supported = 0 };
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static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
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static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
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static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
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#endif /* CONFIG_PCI_DOMAINS */
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/*
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@ -1670,7 +1676,6 @@ static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
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static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
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static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
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static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
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#define dev_is_pci(d) (false)
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#define dev_is_pf(d) (false)
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@ -1954,6 +1959,7 @@ int pci_num_vf(struct pci_dev *dev);
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int pci_vfs_assigned(struct pci_dev *dev);
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int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
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int pci_sriov_get_totalvfs(struct pci_dev *dev);
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int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
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resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
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void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
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@ -1986,6 +1992,7 @@ static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
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{ return 0; }
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static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
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{ return 0; }
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#define pci_sriov_configure_simple NULL
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static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
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{ return 0; }
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static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
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@ -2284,7 +2291,7 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
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return false;
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}
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#if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH)
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#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
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void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
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#endif
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