mirror of
https://github.com/Fishwaldo/Star64_linux.git
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Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', 'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged
This commit is contained in:
Lee Jones
commit
3f979bf8f5
1835 changed files with 32812 additions and 25651 deletions
57
Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32
Normal file
57
Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32
Normal file
|
|
@ -0,0 +1,57 @@
|
||||||
|
What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset
|
||||||
|
KernelVersion: 4.13
|
||||||
|
Contact: fabrice.gasnier@st.com
|
||||||
|
Description:
|
||||||
|
Reading returns the current preset value. Writing sets the
|
||||||
|
preset value. Encoder counts continuously from 0 to preset
|
||||||
|
value, depending on direction (up/down).
|
||||||
|
|
||||||
|
What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available
|
||||||
|
KernelVersion: 4.13
|
||||||
|
Contact: fabrice.gasnier@st.com
|
||||||
|
Description:
|
||||||
|
Reading returns the list possible quadrature modes.
|
||||||
|
|
||||||
|
What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode
|
||||||
|
KernelVersion: 4.13
|
||||||
|
Contact: fabrice.gasnier@st.com
|
||||||
|
Description:
|
||||||
|
Configure the device counter quadrature modes:
|
||||||
|
- non-quadrature:
|
||||||
|
Encoder IN1 input servers as the count input (up
|
||||||
|
direction).
|
||||||
|
- quadrature:
|
||||||
|
Encoder IN1 and IN2 inputs are mixed to get direction
|
||||||
|
and count.
|
||||||
|
|
||||||
|
What: /sys/bus/iio/devices/iio:deviceX/in_count_polarity_available
|
||||||
|
KernelVersion: 4.13
|
||||||
|
Contact: fabrice.gasnier@st.com
|
||||||
|
Description:
|
||||||
|
Reading returns the list possible active edges.
|
||||||
|
|
||||||
|
What: /sys/bus/iio/devices/iio:deviceX/in_count0_polarity
|
||||||
|
KernelVersion: 4.13
|
||||||
|
Contact: fabrice.gasnier@st.com
|
||||||
|
Description:
|
||||||
|
Configure the device encoder/counter active edge:
|
||||||
|
- rising-edge
|
||||||
|
- falling-edge
|
||||||
|
- both-edges
|
||||||
|
|
||||||
|
In non-quadrature mode, device counts up on active edge.
|
||||||
|
In quadrature mode, encoder counting scenarios are as follows:
|
||||||
|
----------------------------------------------------------------
|
||||||
|
| Active | Level on | IN1 signal | IN2 signal |
|
||||||
|
| edge | opposite |------------------------------------------
|
||||||
|
| | signal | Rising | Falling | Rising | Falling |
|
||||||
|
----------------------------------------------------------------
|
||||||
|
| Rising | High -> | Down | - | Up | - |
|
||||||
|
| edge | Low -> | Up | - | Down | - |
|
||||||
|
----------------------------------------------------------------
|
||||||
|
| Falling | High -> | - | Up | - | Down |
|
||||||
|
| edge | Low -> | - | Down | - | Up |
|
||||||
|
----------------------------------------------------------------
|
||||||
|
| Both | High -> | Down | Up | Up | Down |
|
||||||
|
| edges | Low -> | Up | Down | Down | Up |
|
||||||
|
----------------------------------------------------------------
|
||||||
|
|
@ -237,6 +237,14 @@ are the following:
|
||||||
This attribute is not present if the scaling driver in use does not
|
This attribute is not present if the scaling driver in use does not
|
||||||
support it.
|
support it.
|
||||||
|
|
||||||
|
``cpuinfo_cur_freq``
|
||||||
|
Current frequency of the CPUs belonging to this policy as obtained from
|
||||||
|
the hardware (in KHz).
|
||||||
|
|
||||||
|
This is expected to be the frequency the hardware actually runs at.
|
||||||
|
If that frequency cannot be determined, this attribute should not
|
||||||
|
be present.
|
||||||
|
|
||||||
``cpuinfo_max_freq``
|
``cpuinfo_max_freq``
|
||||||
Maximum possible operating frequency the CPUs belonging to this policy
|
Maximum possible operating frequency the CPUs belonging to this policy
|
||||||
can run at (in kHz).
|
can run at (in kHz).
|
||||||
|
|
|
||||||
|
|
@ -343,3 +343,4 @@ Version History
|
||||||
1.11.0 Fix table line argument order
|
1.11.0 Fix table line argument order
|
||||||
(wrong raid10_copies/raid10_format sequence)
|
(wrong raid10_copies/raid10_format sequence)
|
||||||
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
|
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
|
||||||
|
1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,22 @@
|
||||||
* Renesas R-Car SATA
|
* Renesas R-Car SATA
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible : should contain one of the following:
|
- compatible : should contain one or more of the following:
|
||||||
- "renesas,sata-r8a7779" for R-Car H1
|
- "renesas,sata-r8a7779" for R-Car H1
|
||||||
("renesas,rcar-sata" is deprecated)
|
|
||||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||||
- "renesas,sata-r8a7791" for R-Car M2-W
|
- "renesas,sata-r8a7791" for R-Car M2-W
|
||||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||||
- "renesas,sata-r8a7795" for R-Car H3
|
- "renesas,sata-r8a7795" for R-Car H3
|
||||||
|
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||||
|
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||||
|
- "renesas,rcar-sata" is deprecated
|
||||||
|
|
||||||
|
When compatible with the generic version nodes
|
||||||
|
must list the SoC-specific version corresponding
|
||||||
|
to the platform first followed by the generic
|
||||||
|
version.
|
||||||
|
|
||||||
- reg : address and length of the SATA registers;
|
- reg : address and length of the SATA registers;
|
||||||
- interrupts : must consist of one interrupt specifier.
|
- interrupts : must consist of one interrupt specifier.
|
||||||
- clocks : must contain a reference to the functional clock.
|
- clocks : must contain a reference to the functional clock.
|
||||||
|
|
@ -16,7 +24,7 @@ Required properties:
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
sata0: sata@ee300000 {
|
sata0: sata@ee300000 {
|
||||||
compatible = "renesas,sata-r8a7791";
|
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
|
||||||
reg = <0 0xee300000 0 0x2000>;
|
reg = <0 0xee300000 0 0x2000>;
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
|
||||||
|
|
@ -8,7 +8,6 @@ Required properties:
|
||||||
|
|
||||||
Optional properties:
|
Optional properties:
|
||||||
- clocks: Reference to the crypto engine clock.
|
- clocks: Reference to the crypto engine clock.
|
||||||
- dma-mask: The address mask limitation. Defaults to 64.
|
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
|
|
@ -24,6 +23,5 @@ Example:
|
||||||
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
|
||||||
"eip";
|
"eip";
|
||||||
clocks = <&cpm_syscon0 1 26>;
|
clocks = <&cpm_syscon0 1 26>;
|
||||||
dma-mask = <0xff 0xffffffff>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
5
Documentation/devicetree/bindings/gpio/gpio-exar.txt
Normal file
5
Documentation/devicetree/bindings/gpio/gpio-exar.txt
Normal file
|
|
@ -0,0 +1,5 @@
|
||||||
|
Exportable MPIO interface of Exar UART chips
|
||||||
|
|
||||||
|
Required properties of the device:
|
||||||
|
- exar,first-pin: first exportable pins (0..15)
|
||||||
|
- ngpios: number of exportable pins (1..16)
|
||||||
|
|
@ -40,7 +40,7 @@ Optional properties:
|
||||||
Example for a Mali-T760:
|
Example for a Mali-T760:
|
||||||
|
|
||||||
gpu@ffa30000 {
|
gpu@ffa30000 {
|
||||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||||
reg = <0xffa30000 0x10000>;
|
reg = <0xffa30000 0x10000>;
|
||||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
|
||||||
|
|
||||||
|
STM32 Low-Power Timer provides several counter modes. It can be used as:
|
||||||
|
- quadrature encoder to detect angular position and direction of rotary
|
||||||
|
elements, from IN1 and IN2 input signals.
|
||||||
|
- simple counter from IN1 input signal.
|
||||||
|
|
||||||
|
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||||
|
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "st,stm32-lptimer-counter".
|
||||||
|
- pinctrl-names: Set to "default".
|
||||||
|
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||||
|
to set IN1/IN2 pins in mode of operation for Low-Power
|
||||||
|
Timer input on external pin.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
timer@40002400 {
|
||||||
|
compatible = "st,stm32-lptimer";
|
||||||
|
...
|
||||||
|
counter {
|
||||||
|
compatible = "st,stm32-lptimer-counter";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&lptim1_in_pins>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
STMicroelectronics STM32 Low-Power Timer Trigger
|
||||||
|
|
||||||
|
STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
|
||||||
|
by STM32 internal ADC and/or DAC.
|
||||||
|
|
||||||
|
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||||
|
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "st,stm32-lptimer-trigger".
|
||||||
|
- reg: Identify trigger hardware block. Must be 0, 1 or 2
|
||||||
|
respectively for lptimer1, lptimer2 or lptimer3
|
||||||
|
trigger output.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
timer@40002400 {
|
||||||
|
compatible = "st,stm32-lptimer";
|
||||||
|
...
|
||||||
|
trigger@0 {
|
||||||
|
compatible = "st,stm32-lptimer-trigger";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -1,11 +1,14 @@
|
||||||
RK8XX Power Management Integrated Circuit
|
RK8XX Power Management Integrated Circuit
|
||||||
|
|
||||||
The rk8xx family current members:
|
The rk8xx family current members:
|
||||||
|
rk805
|
||||||
rk808
|
rk808
|
||||||
rk818
|
rk818
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: "rockchip,rk808", "rockchip,rk818"
|
- compatible: "rockchip,rk805"
|
||||||
|
- compatible: "rockchip,rk808"
|
||||||
|
- compatible: "rockchip,rk818"
|
||||||
- reg: I2C slave address
|
- reg: I2C slave address
|
||||||
- interrupt-parent: The parent interrupt controller.
|
- interrupt-parent: The parent interrupt controller.
|
||||||
- interrupts: the interrupt outputs of the controller.
|
- interrupts: the interrupt outputs of the controller.
|
||||||
|
|
@ -18,6 +21,14 @@ Optional properties:
|
||||||
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
|
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
|
||||||
the system power.
|
the system power.
|
||||||
|
|
||||||
|
Optional RK805 properties:
|
||||||
|
- vcc1-supply: The input supply for DCDC_REG1
|
||||||
|
- vcc2-supply: The input supply for DCDC_REG2
|
||||||
|
- vcc3-supply: The input supply for DCDC_REG3
|
||||||
|
- vcc4-supply: The input supply for DCDC_REG4
|
||||||
|
- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
|
||||||
|
- vcc6-supply: The input supply for LDO_REG3
|
||||||
|
|
||||||
Optional RK808 properties:
|
Optional RK808 properties:
|
||||||
- vcc1-supply: The input supply for DCDC_REG1
|
- vcc1-supply: The input supply for DCDC_REG1
|
||||||
- vcc2-supply: The input supply for DCDC_REG2
|
- vcc2-supply: The input supply for DCDC_REG2
|
||||||
|
|
@ -56,6 +67,15 @@ by a child node of the 'regulators' node.
|
||||||
/* standard regulator bindings here */
|
/* standard regulator bindings here */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
Following regulators of the RK805 PMIC regulators are supported. Note that
|
||||||
|
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||||
|
number as described in RK805 datasheet.
|
||||||
|
|
||||||
|
- DCDC_REGn
|
||||||
|
- valid values for n are 1 to 4.
|
||||||
|
- LDO_REGn
|
||||||
|
- valid values for n are 1 to 3
|
||||||
|
|
||||||
Following regulators of the RK808 PMIC block are supported. Note that
|
Following regulators of the RK808 PMIC block are supported. Note that
|
||||||
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
|
||||||
number as described in RK808 datasheet.
|
number as described in RK808 datasheet.
|
||||||
|
|
|
||||||
48
Documentation/devicetree/bindings/mfd/stm32-lptimer.txt
Normal file
48
Documentation/devicetree/bindings/mfd/stm32-lptimer.txt
Normal file
|
|
@ -0,0 +1,48 @@
|
||||||
|
STMicroelectronics STM32 Low-Power Timer
|
||||||
|
|
||||||
|
The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
|
||||||
|
functions:
|
||||||
|
- PWM output (with programmable prescaler, configurable polarity)
|
||||||
|
- Quadrature encoder, counter
|
||||||
|
- Trigger source for STM32 ADC/DAC (LPTIM_OUT)
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
- compatible: Must be "st,stm32-lptimer".
|
||||||
|
- reg: Offset and length of the device's register set.
|
||||||
|
- clocks: Phandle to the clock used by the LP Timer module.
|
||||||
|
- clock-names: Must be "mux".
|
||||||
|
- #address-cells: Should be '<1>'.
|
||||||
|
- #size-cells: Should be '<0>'.
|
||||||
|
|
||||||
|
Optional subnodes:
|
||||||
|
- pwm: See ../pwm/pwm-stm32-lp.txt
|
||||||
|
- counter: See ../iio/timer/stm32-lptimer-cnt.txt
|
||||||
|
- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
|
||||||
|
|
||||||
|
Example:
|
||||||
|
|
||||||
|
timer@40002400 {
|
||||||
|
compatible = "st,stm32-lptimer";
|
||||||
|
reg = <0x40002400 0x400>;
|
||||||
|
clocks = <&timer_clk>;
|
||||||
|
clock-names = "mux";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm-lp";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&lppwm1_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
trigger@0 {
|
||||||
|
compatible = "st,stm32-lptimer-trigger";
|
||||||
|
reg = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
counter {
|
||||||
|
compatible = "st,stm32-lptimer-counter";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&lptim1_in_pins>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -78,7 +78,6 @@ Example:
|
||||||
};
|
};
|
||||||
|
|
||||||
dwmmc0@12200000 {
|
dwmmc0@12200000 {
|
||||||
num-slots = <1>;
|
|
||||||
cap-mmc-highspeed;
|
cap-mmc-highspeed;
|
||||||
cap-sd-highspeed;
|
cap-sd-highspeed;
|
||||||
broken-cd;
|
broken-cd;
|
||||||
|
|
|
||||||
|
|
@ -24,6 +24,5 @@ Example:
|
||||||
|
|
||||||
fifo-depth = <0x20>;
|
fifo-depth = <0x20>;
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
num-slots = <1>;
|
|
||||||
disable-wp;
|
disable-wp;
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -36,7 +36,6 @@ Example:
|
||||||
|
|
||||||
/* Board portion */
|
/* Board portion */
|
||||||
dwmmc0@fcd03000 {
|
dwmmc0@fcd03000 {
|
||||||
num-slots = <1>;
|
|
||||||
vmmc-supply = <&ldo12>;
|
vmmc-supply = <&ldo12>;
|
||||||
fifo-depth = <0x100>;
|
fifo-depth = <0x100>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
@ -52,7 +51,6 @@ Example:
|
||||||
|
|
||||||
dwmmc_1: dwmmc1@f723e000 {
|
dwmmc_1: dwmmc1@f723e000 {
|
||||||
compatible = "hisilicon,hi6220-dw-mshc";
|
compatible = "hisilicon,hi6220-dw-mshc";
|
||||||
num-slots = <0x1>;
|
|
||||||
bus-width = <0x4>;
|
bus-width = <0x4>;
|
||||||
disable-wp;
|
disable-wp;
|
||||||
cap-sd-highspeed;
|
cap-sd-highspeed;
|
||||||
|
|
|
||||||
|
|
@ -12,12 +12,12 @@ Required Properties:
|
||||||
* #address-cells: should be 1.
|
* #address-cells: should be 1.
|
||||||
* #size-cells: should be 0.
|
* #size-cells: should be 0.
|
||||||
|
|
||||||
# Slots: The slot specific information are contained within child-nodes with
|
# Slots (DEPRECATED): The slot specific information are contained within
|
||||||
each child-node representing a supported slot. There should be atleast one
|
child-nodes with each child-node representing a supported slot. There should
|
||||||
child node representing a card slot. The name of the child node representing
|
be atleast one child node representing a card slot. The name of the child node
|
||||||
the slot is recommended to be slot@n where n is the unique number of the slot
|
representing the slot is recommended to be slot@n where n is the unique number
|
||||||
connected to the controller. The following are optional properties which
|
of the slot connected to the controller. The following are optional properties
|
||||||
can be included in the slot child node.
|
which can be included in the slot child node.
|
||||||
|
|
||||||
* reg: specifies the physical slot number. The valid values of this
|
* reg: specifies the physical slot number. The valid values of this
|
||||||
property is 0 to (num-slots -1), where num-slots is the value
|
property is 0 to (num-slots -1), where num-slots is the value
|
||||||
|
|
@ -63,7 +63,7 @@ Optional properties:
|
||||||
clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
|
clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
|
||||||
(Use the "max-frequency" instead of "clock-freq-min-max".)
|
(Use the "max-frequency" instead of "clock-freq-min-max".)
|
||||||
|
|
||||||
* num-slots: specifies the number of slots supported by the controller.
|
* num-slots (DEPRECATED): specifies the number of slots supported by the controller.
|
||||||
The number of physical slots actually used could be equal or less than the
|
The number of physical slots actually used could be equal or less than the
|
||||||
value specified by num-slots. If this property is not specified, the value
|
value specified by num-slots. If this property is not specified, the value
|
||||||
of num-slot property is assumed to be 1.
|
of num-slot property is assumed to be 1.
|
||||||
|
|
@ -124,7 +124,6 @@ board specific portions as listed below.
|
||||||
dwmmc0@12200000 {
|
dwmmc0@12200000 {
|
||||||
clock-frequency = <400000000>;
|
clock-frequency = <400000000>;
|
||||||
clock-freq-min-max = <400000 200000000>;
|
clock-freq-min-max = <400000 200000000>;
|
||||||
num-slots = <1>;
|
|
||||||
broken-cd;
|
broken-cd;
|
||||||
fifo-depth = <0x80>;
|
fifo-depth = <0x80>;
|
||||||
card-detect-delay = <200>;
|
card-detect-delay = <200>;
|
||||||
|
|
@ -139,7 +138,6 @@ board specific portions as listed below.
|
||||||
dwmmc0@12200000 {
|
dwmmc0@12200000 {
|
||||||
clock-frequency = <400000000>;
|
clock-frequency = <400000000>;
|
||||||
clock-freq-min-max = <400000 200000000>;
|
clock-freq-min-max = <400000 200000000>;
|
||||||
num-slots = <1>;
|
|
||||||
broken-cd;
|
broken-cd;
|
||||||
fifo-depth = <0x80>;
|
fifo-depth = <0x80>;
|
||||||
card-detect-delay = <200>;
|
card-detect-delay = <200>;
|
||||||
|
|
|
||||||
|
|
@ -25,7 +25,6 @@ Example:
|
||||||
clock-frequency = <50000000>;
|
clock-frequency = <50000000>;
|
||||||
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
|
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
|
||||||
clock-names = "biu", "ciu";
|
clock-names = "biu", "ciu";
|
||||||
num-slots = <1>;
|
|
||||||
max-frequency = <50000000>;
|
max-frequency = <50000000>;
|
||||||
cap-sdio-irq;
|
cap-sdio-irq;
|
||||||
cap-sd-highspeed;
|
cap-sd-highspeed;
|
||||||
|
|
|
||||||
|
|
@ -11,6 +11,7 @@ Required properties:
|
||||||
- reg-names: Names of the registers.
|
- reg-names: Names of the registers.
|
||||||
"amac_base": Address and length of the GMAC registers
|
"amac_base": Address and length of the GMAC registers
|
||||||
"idm_base": Address and length of the GMAC IDM registers
|
"idm_base": Address and length of the GMAC IDM registers
|
||||||
|
(required for NSP and Northstar2)
|
||||||
"nicpm_base": Address and length of the NIC Port Manager
|
"nicpm_base": Address and length of the NIC Port Manager
|
||||||
registers (required for Northstar2)
|
registers (required for Northstar2)
|
||||||
- interrupts: Interrupt number
|
- interrupts: Interrupt number
|
||||||
|
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
Broadcom GMAC Ethernet Controller Device Tree Bindings
|
|
||||||
-------------------------------------------------------------
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: "brcm,bgmac-nsp"
|
|
||||||
- reg: Address and length of the GMAC registers,
|
|
||||||
Address and length of the GMAC IDM registers
|
|
||||||
- reg-names: Names of the registers. Must have both "gmac_base" and
|
|
||||||
"idm_base"
|
|
||||||
- interrupts: Interrupt number
|
|
||||||
|
|
||||||
Optional properties:
|
|
||||||
- mac-address: See ethernet.txt file in the same directory
|
|
||||||
|
|
||||||
Examples:
|
|
||||||
|
|
||||||
gmac0: ethernet@18022000 {
|
|
||||||
compatible = "brcm,bgmac-nsp";
|
|
||||||
reg = <0x18022000 0x1000>,
|
|
||||||
<0x18110000 0x1000>;
|
|
||||||
reg-names = "gmac_base", "idm_base";
|
|
||||||
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
@ -1,84 +0,0 @@
|
||||||
* Allwinner sun8i GMAC ethernet controller
|
|
||||||
|
|
||||||
This device is a platform glue layer for stmmac.
|
|
||||||
Please see stmmac.txt for the other unchanged properties.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: should be one of the following string:
|
|
||||||
"allwinner,sun8i-a83t-emac"
|
|
||||||
"allwinner,sun8i-h3-emac"
|
|
||||||
"allwinner,sun8i-v3s-emac"
|
|
||||||
"allwinner,sun50i-a64-emac"
|
|
||||||
- reg: address and length of the register for the device.
|
|
||||||
- interrupts: interrupt for the device
|
|
||||||
- interrupt-names: should be "macirq"
|
|
||||||
- clocks: A phandle to the reference clock for this device
|
|
||||||
- clock-names: should be "stmmaceth"
|
|
||||||
- resets: A phandle to the reset control for this device
|
|
||||||
- reset-names: should be "stmmaceth"
|
|
||||||
- phy-mode: See ethernet.txt
|
|
||||||
- phy-handle: See ethernet.txt
|
|
||||||
- #address-cells: shall be 1
|
|
||||||
- #size-cells: shall be 0
|
|
||||||
- syscon: A phandle to the syscon of the SoC with one of the following
|
|
||||||
compatible string:
|
|
||||||
- allwinner,sun8i-h3-system-controller
|
|
||||||
- allwinner,sun8i-v3s-system-controller
|
|
||||||
- allwinner,sun50i-a64-system-controller
|
|
||||||
- allwinner,sun8i-a83t-system-controller
|
|
||||||
|
|
||||||
Optional properties:
|
|
||||||
- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
|
|
||||||
- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
|
|
||||||
Both delay properties need to be a multiple of 100. They control the delay for
|
|
||||||
external PHY.
|
|
||||||
|
|
||||||
Optional properties for the following compatibles:
|
|
||||||
- "allwinner,sun8i-h3-emac",
|
|
||||||
- "allwinner,sun8i-v3s-emac":
|
|
||||||
- allwinner,leds-active-low: EPHY LEDs are active low
|
|
||||||
|
|
||||||
Required child node of emac:
|
|
||||||
- mdio bus node: should be named mdio
|
|
||||||
|
|
||||||
Required properties of the mdio node:
|
|
||||||
- #address-cells: shall be 1
|
|
||||||
- #size-cells: shall be 0
|
|
||||||
|
|
||||||
The device node referenced by "phy" or "phy-handle" should be a child node
|
|
||||||
of the mdio node. See phy.txt for the generic PHY bindings.
|
|
||||||
|
|
||||||
Required properties of the phy node with the following compatibles:
|
|
||||||
- "allwinner,sun8i-h3-emac",
|
|
||||||
- "allwinner,sun8i-v3s-emac":
|
|
||||||
- clocks: a phandle to the reference clock for the EPHY
|
|
||||||
- resets: a phandle to the reset control for the EPHY
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
emac: ethernet@1c0b000 {
|
|
||||||
compatible = "allwinner,sun8i-h3-emac";
|
|
||||||
syscon = <&syscon>;
|
|
||||||
reg = <0x01c0b000 0x104>;
|
|
||||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-names = "macirq";
|
|
||||||
resets = <&ccu RST_BUS_EMAC>;
|
|
||||||
reset-names = "stmmaceth";
|
|
||||||
clocks = <&ccu CLK_BUS_EMAC>;
|
|
||||||
clock-names = "stmmaceth";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
phy-handle = <&int_mii_phy>;
|
|
||||||
phy-mode = "mii";
|
|
||||||
allwinner,leds-active-low;
|
|
||||||
mdio: mdio {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
int_mii_phy: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
clocks = <&ccu CLK_BUS_EPHY>;
|
|
||||||
resets = <&ccu RST_BUS_EPHY>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
@ -4,7 +4,7 @@ Required properties:
|
||||||
- compatible: Should be one of the following.
|
- compatible: Should be one of the following.
|
||||||
- "rockchip,rk3066a-efuse" - for RK3066a SoCs.
|
- "rockchip,rk3066a-efuse" - for RK3066a SoCs.
|
||||||
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
|
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
|
||||||
- "rockchip,rk322x-efuse" - for RK322x SoCs.
|
- "rockchip,rk3228-efuse" - for RK3228 SoCs.
|
||||||
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
|
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
|
||||||
- "rockchip,rk3399-efuse" - for RK3399 SoCs.
|
- "rockchip,rk3399-efuse" - for RK3399 SoCs.
|
||||||
- reg: Should contain the registers location and exact eFuse size
|
- reg: Should contain the registers location and exact eFuse size
|
||||||
|
|
|
||||||
63
Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt
Normal file
63
Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt
Normal file
|
|
@ -0,0 +1,63 @@
|
||||||
|
Pincontrol driver for RK805 Power management IC.
|
||||||
|
|
||||||
|
RK805 has 2 pins which can be configured as GPIO output only.
|
||||||
|
|
||||||
|
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
|
||||||
|
for details of the common pinctrl bindings used by client devices,
|
||||||
|
including the meaning of the phrase "pin configuration node".
|
||||||
|
|
||||||
|
Optional Pinmux properties:
|
||||||
|
--------------------------
|
||||||
|
Following properties are required if default setting of pins are required
|
||||||
|
at boot.
|
||||||
|
- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
|
||||||
|
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
|
||||||
|
<pinctrl-binding.txt>.
|
||||||
|
|
||||||
|
The pin configurations are defined as child of the pinctrl states node. Each
|
||||||
|
sub-node have following properties:
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
------------------
|
||||||
|
- #gpio-cells: Should be two. The first cell is the pin number and the
|
||||||
|
second is the GPIO flags.
|
||||||
|
|
||||||
|
- gpio-controller: Marks the device node as a GPIO controller.
|
||||||
|
|
||||||
|
- pins: List of pins. Valid values of pins properties are: gpio0, gpio1.
|
||||||
|
|
||||||
|
First 2 properties must be added in the RK805 PMIC node, documented in
|
||||||
|
Documentation/devicetree/bindings/mfd/rk808.txt
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
-------------------
|
||||||
|
Following are optional properties defined as pinmux DT binding document
|
||||||
|
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
|
||||||
|
on default.
|
||||||
|
function,
|
||||||
|
output-low,
|
||||||
|
output-high.
|
||||||
|
|
||||||
|
Valid values for function properties are: gpio.
|
||||||
|
|
||||||
|
Theres is also not customised properties for any GPIO.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
--------
|
||||||
|
rk805: rk805@18 {
|
||||||
|
compatible = "rockchip,rk805";
|
||||||
|
...
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pmic_int_l>, <&rk805_default>;
|
||||||
|
|
||||||
|
rk805_default: pinmux {
|
||||||
|
gpio01 {
|
||||||
|
pins = "gpio0", "gpio1";
|
||||||
|
function = "gpio";
|
||||||
|
output-high;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -1,13 +1,20 @@
|
||||||
* Broadcom Digital Timing Engine(DTE) based PTP clock driver
|
* Broadcom Digital Timing Engine(DTE) based PTP clock
|
||||||
|
|
||||||
Required properties:
|
Required properties:
|
||||||
- compatible: should be "brcm,ptp-dte"
|
- compatible: should contain the core compatibility string
|
||||||
|
and the SoC compatibility string. The SoC
|
||||||
|
compatibility string is to handle SoC specific
|
||||||
|
hardware differences.
|
||||||
|
Core compatibility string:
|
||||||
|
"brcm,ptp-dte"
|
||||||
|
SoC compatibility strings:
|
||||||
|
"brcm,iproc-ptp-dte" - for iproc based SoC's
|
||||||
- reg: address and length of the DTE block's NCO registers
|
- reg: address and length of the DTE block's NCO registers
|
||||||
|
|
||||||
Example:
|
Example:
|
||||||
|
|
||||||
ptp_dte: ptp_dte@180af650 {
|
ptp: ptp-dte@180af650 {
|
||||||
compatible = "brcm,ptp-dte";
|
compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
|
||||||
reg = <0x180af650 0x10>;
|
reg = <0x180af650 0x10>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
24
Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
Normal file
24
Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
Normal file
|
|
@ -0,0 +1,24 @@
|
||||||
|
STMicroelectronics STM32 Low-Power Timer PWM
|
||||||
|
|
||||||
|
STM32 Low-Power Timer provides single channel PWM.
|
||||||
|
|
||||||
|
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||||
|
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||||
|
|
||||||
|
Required parameters:
|
||||||
|
- compatible: Must be "st,stm32-pwm-lp".
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- pinctrl-names: Set to "default".
|
||||||
|
- pinctrl-0: Phandle pointing to pin configuration node for PWM.
|
||||||
|
|
||||||
|
Example:
|
||||||
|
timer@40002400 {
|
||||||
|
compatible = "st,stm32-lptimer";
|
||||||
|
...
|
||||||
|
pwm {
|
||||||
|
compatible = "st,stm32-pwm-lp";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&lppwm1_pins>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -9,7 +9,6 @@ Optional properties:
|
||||||
- fsl,irda-mode : Indicate the uart supports irda mode
|
- fsl,irda-mode : Indicate the uart supports irda mode
|
||||||
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
|
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
|
||||||
in DCE mode by default.
|
in DCE mode by default.
|
||||||
- fsl,dma-size : Indicate the size of the DMA buffer and its periods
|
|
||||||
|
|
||||||
Please check Documentation/devicetree/bindings/serial/serial.txt
|
Please check Documentation/devicetree/bindings/serial/serial.txt
|
||||||
for the complete list of generic properties.
|
for the complete list of generic properties.
|
||||||
|
|
@ -29,5 +28,4 @@ uart1: serial@73fbc000 {
|
||||||
interrupts = <31>;
|
interrupts = <31>;
|
||||||
uart-has-rtscts;
|
uart-has-rtscts;
|
||||||
fsl,dte-mode;
|
fsl,dte-mode;
|
||||||
fsl,dma-size = <1024 4>;
|
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -27,5 +27,11 @@ You have to add the following kernel parameters in your elilo.conf:
|
||||||
Macbook Pro 17", iMac 20" :
|
Macbook Pro 17", iMac 20" :
|
||||||
video=efifb:i20
|
video=efifb:i20
|
||||||
|
|
||||||
|
Accepted options:
|
||||||
|
|
||||||
|
nowc Don't map the framebuffer write combined. This can be used
|
||||||
|
to workaround side-effects and slowdowns on other CPU cores
|
||||||
|
when large amounts of console data are written.
|
||||||
|
|
||||||
--
|
--
|
||||||
Edgar Hucek <gimli@dark-green.com>
|
Edgar Hucek <gimli@dark-green.com>
|
||||||
|
|
|
||||||
|
|
@ -459,7 +459,7 @@ pin controller?
|
||||||
|
|
||||||
This is done by registering "ranges" of pins, which are essentially
|
This is done by registering "ranges" of pins, which are essentially
|
||||||
cross-reference tables. These are described in
|
cross-reference tables. These are described in
|
||||||
Documentation/pinctrl.txt
|
Documentation/driver-api/pinctl.rst
|
||||||
|
|
||||||
While the pin allocation is totally managed by the pinctrl subsystem,
|
While the pin allocation is totally managed by the pinctrl subsystem,
|
||||||
gpio (under gpiolib) is still maintained by gpio drivers. It may happen
|
gpio (under gpiolib) is still maintained by gpio drivers. It may happen
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,31 @@
|
||||||
Digital TV (DVB) devices
|
Digital TV (DVB) devices
|
||||||
------------------------
|
------------------------
|
||||||
|
|
||||||
|
Digital TV devices are implemented by several different drivers:
|
||||||
|
|
||||||
|
- A bridge driver that is responsible to talk with the bus where the other
|
||||||
|
devices are connected (PCI, USB, SPI), bind to the other drivers and
|
||||||
|
implement the digital demux logic (either in software or in hardware);
|
||||||
|
|
||||||
|
- Frontend drivers that are usually implemented as two separate drivers:
|
||||||
|
|
||||||
|
- A tuner driver that implements the logic with commands the part of the
|
||||||
|
hardware with is reponsible to tune into a digital TV transponder or
|
||||||
|
physical channel. The output of a tuner is usually a baseband or
|
||||||
|
Intermediate Frequency (IF) signal;
|
||||||
|
|
||||||
|
- A demodulator driver (a.k.a "demod") that implements the logic with
|
||||||
|
commands the digital TV decoding hardware. The output of a demod is
|
||||||
|
a digital stream, with multiple audio, video and data channels typically
|
||||||
|
multiplexed using MPEG Transport Stream [#f1]_.
|
||||||
|
|
||||||
|
On most hardware, the frontend drivers talk with the bridge driver using an
|
||||||
|
I2C bus.
|
||||||
|
|
||||||
|
.. [#f1] Some standards use TCP/IP for multiplexing data, like DVB-H (an
|
||||||
|
abandoned standard, not used anymore) and ATSC version 3.0 current
|
||||||
|
proposals. Currently, the DVB subsystem doesn't implement those standards.
|
||||||
|
|
||||||
Digital TV Common functions
|
Digital TV Common functions
|
||||||
---------------------------
|
---------------------------
|
||||||
|
|
||||||
|
|
@ -55,8 +80,141 @@ Digital TV Frontend
|
||||||
The Digital TV Frontend kABI defines a driver-internal interface for
|
The Digital TV Frontend kABI defines a driver-internal interface for
|
||||||
registering low-level, hardware specific driver to a hardware independent
|
registering low-level, hardware specific driver to a hardware independent
|
||||||
frontend layer. It is only of interest for Digital TV device driver writers.
|
frontend layer. It is only of interest for Digital TV device driver writers.
|
||||||
The header file for this API is named dvb_frontend.h and located in
|
The header file for this API is named ``dvb_frontend.h`` and located in
|
||||||
drivers/media/dvb-core.
|
``drivers/media/dvb-core``.
|
||||||
|
|
||||||
|
Demodulator driver
|
||||||
|
^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
The demodulator driver is responsible to talk with the decoding part of the
|
||||||
|
hardware. Such driver should implement :c:type:`dvb_frontend_ops`, with
|
||||||
|
tells what type of digital TV standards are supported, and points to a
|
||||||
|
series of functions that allow the DVB core to command the hardware via
|
||||||
|
the code under ``drivers/media/dvb-core/dvb_frontend.c``.
|
||||||
|
|
||||||
|
A typical example of such struct in a driver ``foo`` is::
|
||||||
|
|
||||||
|
static struct dvb_frontend_ops foo_ops = {
|
||||||
|
.delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
|
||||||
|
.info = {
|
||||||
|
.name = "foo DVB-T/T2/C driver",
|
||||||
|
.caps = FE_CAN_FEC_1_2 |
|
||||||
|
FE_CAN_FEC_2_3 |
|
||||||
|
FE_CAN_FEC_3_4 |
|
||||||
|
FE_CAN_FEC_5_6 |
|
||||||
|
FE_CAN_FEC_7_8 |
|
||||||
|
FE_CAN_FEC_AUTO |
|
||||||
|
FE_CAN_QPSK |
|
||||||
|
FE_CAN_QAM_16 |
|
||||||
|
FE_CAN_QAM_32 |
|
||||||
|
FE_CAN_QAM_64 |
|
||||||
|
FE_CAN_QAM_128 |
|
||||||
|
FE_CAN_QAM_256 |
|
||||||
|
FE_CAN_QAM_AUTO |
|
||||||
|
FE_CAN_TRANSMISSION_MODE_AUTO |
|
||||||
|
FE_CAN_GUARD_INTERVAL_AUTO |
|
||||||
|
FE_CAN_HIERARCHY_AUTO |
|
||||||
|
FE_CAN_MUTE_TS |
|
||||||
|
FE_CAN_2G_MODULATION,
|
||||||
|
.frequency_min = 42000000, /* Hz */
|
||||||
|
.frequency_max = 1002000000, /* Hz */
|
||||||
|
.symbol_rate_min = 870000,
|
||||||
|
.symbol_rate_max = 11700000
|
||||||
|
},
|
||||||
|
.init = foo_init,
|
||||||
|
.sleep = foo_sleep,
|
||||||
|
.release = foo_release,
|
||||||
|
.set_frontend = foo_set_frontend,
|
||||||
|
.get_frontend = foo_get_frontend,
|
||||||
|
.read_status = foo_get_status_and_stats,
|
||||||
|
.tune = foo_tune,
|
||||||
|
.i2c_gate_ctrl = foo_i2c_gate_ctrl,
|
||||||
|
.get_frontend_algo = foo_get_algo,
|
||||||
|
};
|
||||||
|
|
||||||
|
A typical example of such struct in a driver ``bar`` meant to be used on
|
||||||
|
Satellite TV reception is::
|
||||||
|
|
||||||
|
static const struct dvb_frontend_ops bar_ops = {
|
||||||
|
.delsys = { SYS_DVBS, SYS_DVBS2 },
|
||||||
|
.info = {
|
||||||
|
.name = "Bar DVB-S/S2 demodulator",
|
||||||
|
.frequency_min = 500000, /* KHz */
|
||||||
|
.frequency_max = 2500000, /* KHz */
|
||||||
|
.frequency_stepsize = 0,
|
||||||
|
.symbol_rate_min = 1000000,
|
||||||
|
.symbol_rate_max = 45000000,
|
||||||
|
.symbol_rate_tolerance = 500,
|
||||||
|
.caps = FE_CAN_INVERSION_AUTO |
|
||||||
|
FE_CAN_FEC_AUTO |
|
||||||
|
FE_CAN_QPSK,
|
||||||
|
},
|
||||||
|
.init = bar_init,
|
||||||
|
.sleep = bar_sleep,
|
||||||
|
.release = bar_release,
|
||||||
|
.set_frontend = bar_set_frontend,
|
||||||
|
.get_frontend = bar_get_frontend,
|
||||||
|
.read_status = bar_get_status_and_stats,
|
||||||
|
.i2c_gate_ctrl = bar_i2c_gate_ctrl,
|
||||||
|
.get_frontend_algo = bar_get_algo,
|
||||||
|
.tune = bar_tune,
|
||||||
|
|
||||||
|
/* Satellite-specific */
|
||||||
|
.diseqc_send_master_cmd = bar_send_diseqc_msg,
|
||||||
|
.diseqc_send_burst = bar_send_burst,
|
||||||
|
.set_tone = bar_set_tone,
|
||||||
|
.set_voltage = bar_set_voltage,
|
||||||
|
};
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
|
||||||
|
#) For satellite digital TV standards (DVB-S, DVB-S2, ISDB-S), the
|
||||||
|
frequencies are specified in kHz, while, for terrestrial and cable
|
||||||
|
standards, they're specified in Hz. Due to that, if the same frontend
|
||||||
|
supports both types, you'll need to have two separate
|
||||||
|
:c:type:`dvb_frontend_ops` structures, one for each standard.
|
||||||
|
#) The ``.i2c_gate_ctrl`` field is present only when the hardware has
|
||||||
|
allows controlling an I2C gate (either directly of via some GPIO pin),
|
||||||
|
in order to remove the tuner from the I2C bus after a channel is
|
||||||
|
tuned.
|
||||||
|
#) All new drivers should implement the
|
||||||
|
:ref:`DVBv5 statistics <dvbv5_stats>` via ``.read_status``.
|
||||||
|
Yet, there are a number of callbacks meant to get statistics for
|
||||||
|
signal strength, S/N and UCB. Those are there to provide backward
|
||||||
|
compatibility with legacy applications that don't support the DVBv5
|
||||||
|
API. Implementing those callbacks are optional. Those callbacks may be
|
||||||
|
removed in the future, after we have all existing drivers supporting
|
||||||
|
DVBv5 stats.
|
||||||
|
#) Other callbacks are required for satellite TV standards, in order to
|
||||||
|
control LNBf and DiSEqC: ``.diseqc_send_master_cmd``,
|
||||||
|
``.diseqc_send_burst``, ``.set_tone``, ``.set_voltage``.
|
||||||
|
|
||||||
|
.. |delta| unicode:: U+00394
|
||||||
|
|
||||||
|
The ``drivers/media/dvb-core/dvb_frontend.c`` has a kernel thread with is
|
||||||
|
responsible for tuning the device. It supports multiple algoritms to
|
||||||
|
detect a channel, as defined at enum :c:func:`dvbfe_algo`.
|
||||||
|
|
||||||
|
The algorithm to be used is obtained via ``.get_frontend_algo``. If the driver
|
||||||
|
doesn't fill its field at struct :c:type:`dvb_frontend_ops`, it will default to
|
||||||
|
``DVBFE_ALGO_SW``, meaning that the dvb-core will do a zigzag when tuning,
|
||||||
|
e. g. it will try first to use the specified center frequency ``f``,
|
||||||
|
then, it will do ``f`` + |delta|, ``f`` - |delta|, ``f`` + 2 x |delta|,
|
||||||
|
``f`` - 2 x |delta| and so on.
|
||||||
|
|
||||||
|
If the hardware has internally a some sort of zigzag algorithm, you should
|
||||||
|
define a ``.get_frontend_algo`` function that would return ``DVBFE_ALGO_HW``.
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
|
||||||
|
The core frontend support also supports
|
||||||
|
a third type (``DVBFE_ALGO_CUSTOM``), in order to allow the driver to
|
||||||
|
define its own hardware-assisted algorithm. Very few hardware need to
|
||||||
|
use it nowadays. Using ``DVBFE_ALGO_CUSTOM`` require to provide other
|
||||||
|
function callbacks at struct :c:type:`dvb_frontend_ops`.
|
||||||
|
|
||||||
|
Attaching frontend driver to the bridge driver
|
||||||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
Before using the Digital TV frontend core, the bridge driver should attach
|
Before using the Digital TV frontend core, the bridge driver should attach
|
||||||
the frontend demod, tuner and SEC devices and call
|
the frontend demod, tuner and SEC devices and call
|
||||||
|
|
@ -74,6 +232,287 @@ part of their handler for :c:type:`device_driver`.\ ``resume()``.
|
||||||
|
|
||||||
A few other optional functions are provided to handle some special cases.
|
A few other optional functions are provided to handle some special cases.
|
||||||
|
|
||||||
|
.. _dvbv5_stats:
|
||||||
|
|
||||||
|
Digital TV Frontend statistics
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
Introduction
|
||||||
|
^^^^^^^^^^^^
|
||||||
|
|
||||||
|
Digital TV frontends provide a range of
|
||||||
|
:ref:`statistics <frontend-stat-properties>` meant to help tuning the device
|
||||||
|
and measuring the quality of service.
|
||||||
|
|
||||||
|
For each statistics measurement, the driver should set the type of scale used,
|
||||||
|
or ``FE_SCALE_NOT_AVAILABLE`` if the statistics is not available on a given
|
||||||
|
time. Drivers should also provide the number of statistics for each type.
|
||||||
|
that's usually 1 for most video standards [#f2]_.
|
||||||
|
|
||||||
|
Drivers should initialize each statistic counters with length and
|
||||||
|
scale at its init code. For example, if the frontend provides signal
|
||||||
|
strength, it should have, on its init code::
|
||||||
|
|
||||||
|
struct dtv_frontend_properties *c = &state->fe.dtv_property_cache;
|
||||||
|
|
||||||
|
c->strength.len = 1;
|
||||||
|
c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
|
||||||
|
|
||||||
|
And, when the statistics got updated, set the scale::
|
||||||
|
|
||||||
|
c->strength.stat[0].scale = FE_SCALE_DECIBEL;
|
||||||
|
c->strength.stat[0].uvalue = strength;
|
||||||
|
|
||||||
|
.. [#f2] For ISDB-T, it may provide both a global statistics and a per-layer
|
||||||
|
set of statistics. On such cases, len should be equal to 4. The first
|
||||||
|
value corresponds to the global stat; the other ones to each layer, e. g.:
|
||||||
|
|
||||||
|
- c->cnr.stat[0] for global S/N carrier ratio,
|
||||||
|
- c->cnr.stat[1] for Layer A S/N carrier ratio,
|
||||||
|
- c->cnr.stat[2] for layer B S/N carrier ratio,
|
||||||
|
- c->cnr.stat[3] for layer C S/N carrier ratio.
|
||||||
|
|
||||||
|
.. note:: Please prefer to use ``FE_SCALE_DECIBEL`` instead of
|
||||||
|
``FE_SCALE_RELATIVE`` for signal strength and CNR measurements.
|
||||||
|
|
||||||
|
Groups of statistics
|
||||||
|
^^^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
There are several groups of statistics currently supported:
|
||||||
|
|
||||||
|
Signal strength (:ref:`DTV-STAT-SIGNAL-STRENGTH`)
|
||||||
|
- Measures the signal strength level at the analog part of the tuner or
|
||||||
|
demod.
|
||||||
|
|
||||||
|
- Typically obtained from the gain applied to the tuner and/or frontend
|
||||||
|
in order to detect the carrier. When no carrier is detected, the gain is
|
||||||
|
at the maximum value (so, strength is on its minimal).
|
||||||
|
|
||||||
|
- As the gain is visible through the set of registers that adjust the gain,
|
||||||
|
typically, this statistics is always available [#f3]_.
|
||||||
|
|
||||||
|
- Drivers should try to make it available all the times, as this statistics
|
||||||
|
can be used when adjusting an antenna position and to check for troubles
|
||||||
|
at the cabling.
|
||||||
|
|
||||||
|
.. [#f3] On a few devices, the gain keeps floating if no carrier.
|
||||||
|
On such devices, strength report should check first if carrier is
|
||||||
|
detected at the tuner (``FE_HAS_CARRIER``, see :c:type:`fe_status`),
|
||||||
|
and otherwise return the lowest possible value.
|
||||||
|
|
||||||
|
Carrier Signal to Noise ratio (:ref:`DTV-STAT-CNR`)
|
||||||
|
- Signal to Noise ratio for the main carrier.
|
||||||
|
|
||||||
|
- Signal to Noise measurement depends on the device. On some hardware, is
|
||||||
|
available when the main carrier is detected. On those hardware, CNR
|
||||||
|
measurement usually comes from the tuner (e. g. after ``FE_HAS_CARRIER``,
|
||||||
|
see :c:type:`fe_status`).
|
||||||
|
|
||||||
|
On other devices, it requires inner FEC decoding,
|
||||||
|
as the frontend measures it indirectly from other parameters (e. g. after
|
||||||
|
``FE_HAS_VITERBI``, see :c:type:`fe_status`).
|
||||||
|
|
||||||
|
Having it available after inner FEC is more common.
|
||||||
|
|
||||||
|
Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`)
|
||||||
|
- Those counters measure the number of bits and bit errors errors after
|
||||||
|
the forward error correction (FEC) on the inner coding block
|
||||||
|
(after Viterbi, LDPC or other inner code).
|
||||||
|
|
||||||
|
- Due to its nature, those statistics depend on full coding lock
|
||||||
|
(e. g. after ``FE_HAS_SYNC`` or after ``FE_HAS_LOCK``,
|
||||||
|
see :c:type:`fe_status`).
|
||||||
|
|
||||||
|
Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`)
|
||||||
|
- Those counters measure the number of bits and bit errors errors before
|
||||||
|
the forward error correction (FEC) on the inner coding block
|
||||||
|
(before Viterbi, LDPC or other inner code).
|
||||||
|
|
||||||
|
- Not all frontends provide this kind of statistics.
|
||||||
|
|
||||||
|
- Due to its nature, those statistics depend on inner coding lock (e. g.
|
||||||
|
after ``FE_HAS_VITERBI``, see :c:type:`fe_status`).
|
||||||
|
|
||||||
|
Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`)
|
||||||
|
- Those counters measure the number of blocks and block errors errors after
|
||||||
|
the forward error correction (FEC) on the inner coding block
|
||||||
|
(before Viterbi, LDPC or other inner code).
|
||||||
|
|
||||||
|
- Due to its nature, those statistics depend on full coding lock
|
||||||
|
(e. g. after ``FE_HAS_SYNC`` or after
|
||||||
|
``FE_HAS_LOCK``, see :c:type:`fe_status`).
|
||||||
|
|
||||||
|
.. note:: All counters should be monotonically increased as they're
|
||||||
|
collected from the hardware.
|
||||||
|
|
||||||
|
A typical example of the logic that handle status and statistics is::
|
||||||
|
|
||||||
|
static int foo_get_status_and_stats(struct dvb_frontend *fe)
|
||||||
|
{
|
||||||
|
struct foo_state *state = fe->demodulator_priv;
|
||||||
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||||
|
|
||||||
|
int rc;
|
||||||
|
enum fe_status *status;
|
||||||
|
|
||||||
|
/* Both status and strength are always available */
|
||||||
|
rc = foo_read_status(fe, &status);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
rc = foo_read_strength(fe);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
/* Check if CNR is available */
|
||||||
|
if (!(fe->status & FE_HAS_CARRIER))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
rc = foo_read_cnr(fe);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
/* Check if pre-BER stats are available */
|
||||||
|
if (!(fe->status & FE_HAS_VITERBI))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
rc = foo_get_pre_ber(fe);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
/* Check if post-BER stats are available */
|
||||||
|
if (!(fe->status & FE_HAS_SYNC))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
rc = foo_get_post_ber(fe);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dvb_frontend_ops ops = {
|
||||||
|
/* ... */
|
||||||
|
.read_status = foo_get_status_and_stats,
|
||||||
|
};
|
||||||
|
|
||||||
|
Statistics collect
|
||||||
|
^^^^^^^^^^^^^^^^^^
|
||||||
|
|
||||||
|
On almost all frontend hardware, the bit and byte counts are stored by
|
||||||
|
the hardware after a certain amount of time or after the total bit/block
|
||||||
|
counter reaches a certain value (usually programable), for example, on
|
||||||
|
every 1000 ms or after receiving 1,000,000 bits.
|
||||||
|
|
||||||
|
So, if you read the registers too soon, you'll end by reading the same
|
||||||
|
value as in the previous reading, causing the monotonic value to be
|
||||||
|
incremented too often.
|
||||||
|
|
||||||
|
Drivers should take the responsibility to avoid too often reads. That
|
||||||
|
can be done using two approaches:
|
||||||
|
|
||||||
|
if the driver have a bit that indicates when a collected data is ready
|
||||||
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||||
|
|
||||||
|
Driver should check such bit before making the statistics available.
|
||||||
|
|
||||||
|
An example of such behavior can be found at this code snippet (adapted
|
||||||
|
from mb86a20s driver's logic)::
|
||||||
|
|
||||||
|
static int foo_get_pre_ber(struct dvb_frontend *fe)
|
||||||
|
{
|
||||||
|
struct foo_state *state = fe->demodulator_priv;
|
||||||
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||||
|
int rc, bit_error;
|
||||||
|
|
||||||
|
/* Check if the BER measures are already available */
|
||||||
|
rc = foo_read_u8(state, 0x54);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
if (!rc)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Read Bit Error Count */
|
||||||
|
bit_error = foo_read_u32(state, 0x55);
|
||||||
|
if (bit_error < 0)
|
||||||
|
return bit_error;
|
||||||
|
|
||||||
|
/* Read Total Bit Count */
|
||||||
|
rc = foo_read_u32(state, 0x51);
|
||||||
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
|
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||||
|
c->pre_bit_error.stat[0].uvalue += bit_error;
|
||||||
|
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||||
|
c->pre_bit_count.stat[0].uvalue += rc;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
If the driver doesn't provide a statistics available check bit
|
||||||
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||||
|
|
||||||
|
A few devices, however, may not provide a way to check if the stats are
|
||||||
|
available (or the way to check it is unknown). They may not even provide
|
||||||
|
a way to directly read the total number of bits or blocks.
|
||||||
|
|
||||||
|
On those devices, the driver need to ensure that it won't be reading from
|
||||||
|
the register too often and/or estimate the total number of bits/blocks.
|
||||||
|
|
||||||
|
On such drivers, a typical routine to get statistics would be like
|
||||||
|
(adapted from dib8000 driver's logic)::
|
||||||
|
|
||||||
|
struct foo_state {
|
||||||
|
/* ... */
|
||||||
|
|
||||||
|
unsigned long per_jiffies_stats;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int foo_get_pre_ber(struct dvb_frontend *fe)
|
||||||
|
{
|
||||||
|
struct foo_state *state = fe->demodulator_priv;
|
||||||
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||||
|
int rc, bit_error;
|
||||||
|
u64 bits;
|
||||||
|
|
||||||
|
/* Check if time for stats was elapsed */
|
||||||
|
if (!time_after(jiffies, state->per_jiffies_stats))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Next stat should be collected in 1000 ms */
|
||||||
|
state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
|
||||||
|
|
||||||
|
/* Read Bit Error Count */
|
||||||
|
bit_error = foo_read_u32(state, 0x55);
|
||||||
|
if (bit_error < 0)
|
||||||
|
return bit_error;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* On this particular frontend, there's no register that
|
||||||
|
* would provide the number of bits per 1000ms sample. So,
|
||||||
|
* some function would calculate it based on DTV properties
|
||||||
|
*/
|
||||||
|
bits = get_number_of_bits_per_1000ms(fe);
|
||||||
|
|
||||||
|
c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||||||
|
c->pre_bit_error.stat[0].uvalue += bit_error;
|
||||||
|
c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
|
||||||
|
c->pre_bit_count.stat[0].uvalue += bits;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
Please notice that, on both cases, we're getting the statistics using the
|
||||||
|
:c:type:`dvb_frontend_ops` ``.read_status`` callback. The rationale is that
|
||||||
|
the frontend core will automatically call this function periodically
|
||||||
|
(usually, 3 times per second, when the frontend is locked).
|
||||||
|
|
||||||
|
That warrants that we won't miss to collect a counter and increment the
|
||||||
|
monotonic stats at the right time.
|
||||||
|
|
||||||
|
Digital TV Frontend functions and types
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
.. kernel-doc:: drivers/media/dvb-core/dvb_frontend.h
|
.. kernel-doc:: drivers/media/dvb-core/dvb_frontend.h
|
||||||
|
|
||||||
|
|
||||||
|
|
|
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File diff suppressed because it is too large
Load diff
|
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d="m 1162.8865,4739.7407 18.486,0 0,92.4688 18.499,-18.499 18.4859,36.9849 18.499,-36.9849 18.4859,36.9849 18.499,-55.4708 18.4859,55.4708 18.499,-18.4859 18.486,55.4708 18.499,-55.4708 18.4859,18.4859 18.499,36.9849 18.4859,-73.9698 18.499,36.9849 18.4859,-55.4708 0,-55.4839 18.499,0 0,-110.9548 36.985,0 0,110.9548 18.4859,0 0,55.4839 18.499,36.9849 18.4859,-36.9849 18.499,55.4708 18.4859,-18.4859 18.499,55.4708 18.486,-18.4859 0,-129.4537 18.4989,0 0,-110.9548 18.486,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.985,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.486,0 0,110.9548 166.4386,0 0,-110.9548 18.486,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 36.9849,0 0,110.9548 332.8643,0 0,-110.9548 36.9849,0 0,110.9548 18.486,0" /><path
|
d="m 1162.8865,4739.7407 18.486,0 0,92.4688 18.499,-18.499 18.4859,36.9849 18.499,-36.9849 18.4859,36.9849 18.499,-55.4708 18.4859,55.4708 18.499,-18.4859 18.486,55.4708 18.499,-55.4708 18.4859,18.4859 18.499,36.9849 18.4859,-73.9698 18.499,36.9849 18.4859,-55.4708 0,-55.4839 18.499,0 0,-110.9548 36.985,0 0,110.9548 18.4859,0 0,55.4839 18.499,36.9849 18.4859,-36.9849 18.499,55.4708 18.4859,-18.4859 18.499,55.4708 18.486,-18.4859 0,-129.4537 18.4989,0 0,-110.9548 18.486,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.985,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0 0,-110.9548 147.9397,0 0,110.9548 36.9849,0
|
||||||
|
0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.486,0 0,110.9548 166.4386,0 0,-110.9548 18.486,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 18.4859,0 0,110.9548 166.4387,0 0,-110.9548 36.9849,0 0,110.9548 332.8643,0 0,-110.9548 36.9849,0 0,110.9548 18.486,0" /><path
|
||||||
inkscape:connector-curvature="0"
|
inkscape:connector-curvature="0"
|
||||||
id="path190"
|
id="path190"
|
||||||
style="fill:none;stroke:#000000;stroke-width:3.08207679;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1"
|
style="fill:none;stroke:#000000;stroke-width:3.08207679;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1"
|
||||||
|
|
@ -409,7 +412,8 @@
|
||||||
inkscape:connector-curvature="0"
|
inkscape:connector-curvature="0"
|
||||||
id="path200"
|
id="path200"
|
||||||
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|
style="fill:none;stroke:#000000;stroke-width:3.08207679;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1"
|
||||||
d="m 1162.8865,3926.0723 18.486,0 0,55.4839 18.499,92.4558 18.4859,-55.4708 36.9849,36.9849 18.499,-55.4839 18.4859,18.499 18.499,-36.985 18.486,55.4709 18.499,-18.4859 18.4859,-36.985 18.499,18.486 18.4859,36.9849 18.499,-36.9849 18.4859,36.9849 0,-110.9548 18.499,0 0,-110.9547 18.486,0 0,110.9547 166.4386,0 0,-110.9547 18.486,0 0,110.9547 166.4387,0 0,-110.9547 18.4859,0 0,110.9547 166.4387,0 0,-110.9547 18.4859,0 0,110.9547 166.4387,0 0,-110.9547 18.4859,0 0,110.9547 166.4387,0 0,-110.9547 147.9397,0 0,110.9547 36.9849,0 0,-110.9547 147.9397,0 0,110.9547 36.9849,0 0,-110.9547 147.9397,0 0,110.9547 36.985,0 0,-110.9547 147.9397,0 0,110.9547 36.9849,0 0,-110.9547 147.9397,0 0,110.9547 36.9849,0 0,-110.9547 18.4859,0 0,110.9547 166.4387,0 0,-110.9547 18.4859,0 0,110.9547 166.4387,0 0,-110.9547 18.486,0 0,110.9547 166.4386,0 0,-110.9547 18.486,0 0,110.9547 166.4387,0 0,-110.9547 18.4859,0 0,110.9547 351.3633,0 0,-110.9547 36.9849,0 0,110.9547 18.486,0" /><path
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18.4859,0 0,110.9547 351.3633,0 0,-110.9547 36.9849,0 0,110.9547 18.486,0" /><path
|
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inkscape:connector-curvature="0"
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inkscape:connector-curvature="0"
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||||||
id="path202"
|
id="path202"
|
||||||
style="fill:none;stroke:#000000;stroke-width:3.08207679;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1"
|
style="fill:none;stroke:#000000;stroke-width:3.08207679;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:10;stroke-dasharray:none;stroke-opacity:1"
|
||||||
|
|
|
||||||
|
Before Width: | Height: | Size: 59 KiB After Width: | Height: | Size: 58 KiB |
|
|
@ -147,3 +147,9 @@ appropriately. The generic error codes are described at the
|
||||||
EINVAL
|
EINVAL
|
||||||
The struct :c:type:`v4l2_format` ``type`` field is
|
The struct :c:type:`v4l2_format` ``type`` field is
|
||||||
invalid or the requested buffer type not supported.
|
invalid or the requested buffer type not supported.
|
||||||
|
|
||||||
|
EBUSY
|
||||||
|
The device is busy and cannot change the format. This could be
|
||||||
|
because or the device is streaming or buffers are allocated or
|
||||||
|
queued to the driver. Relevant for :ref:`VIDIOC_S_FMT
|
||||||
|
<VIDIOC_G_FMT>` only.
|
||||||
|
|
|
||||||
|
|
@ -607,8 +607,9 @@ References
|
||||||
|
|
||||||
Authors
|
Authors
|
||||||
-------
|
-------
|
||||||
Steve Longerbeam <steve_longerbeam@mentor.com>
|
|
||||||
Philipp Zabel <kernel@pengutronix.de>
|
- Steve Longerbeam <steve_longerbeam@mentor.com>
|
||||||
Russell King <linux@armlinux.org.uk>
|
- Philipp Zabel <kernel@pengutronix.de>
|
||||||
|
- Russell King <linux@armlinux.org.uk>
|
||||||
|
|
||||||
Copyright (C) 2012-2017 Mentor Graphics Inc.
|
Copyright (C) 2012-2017 Mentor Graphics Inc.
|
||||||
|
|
|
||||||
|
|
@ -41,6 +41,7 @@ For more details see the file COPYING in the source distribution of Linux.
|
||||||
cx88
|
cx88
|
||||||
davinci-vpbe
|
davinci-vpbe
|
||||||
fimc
|
fimc
|
||||||
|
imx
|
||||||
ivtv
|
ivtv
|
||||||
max2175
|
max2175
|
||||||
meye
|
meye
|
||||||
|
|
|
||||||
|
|
@ -228,7 +228,7 @@ Learning on the device port should be enabled, as well as learning_sync:
|
||||||
bridge link set dev DEV learning on self
|
bridge link set dev DEV learning on self
|
||||||
bridge link set dev DEV learning_sync on self
|
bridge link set dev DEV learning_sync on self
|
||||||
|
|
||||||
Learning_sync attribute enables syncing of the learned/forgotton FDB entry to
|
Learning_sync attribute enables syncing of the learned/forgotten FDB entry to
|
||||||
the bridge's FDB. It's possible, but not optimal, to enable learning on the
|
the bridge's FDB. It's possible, but not optimal, to enable learning on the
|
||||||
device port and on the bridge port, and disable learning_sync.
|
device port and on the bridge port, and disable learning_sync.
|
||||||
|
|
||||||
|
|
@ -245,7 +245,7 @@ the responsibility of the port driver/device to age out these entries. If the
|
||||||
port device supports ageing, when the FDB entry expires, it will notify the
|
port device supports ageing, when the FDB entry expires, it will notify the
|
||||||
driver which in turn will notify the bridge with SWITCHDEV_FDB_DEL. If the
|
driver which in turn will notify the bridge with SWITCHDEV_FDB_DEL. If the
|
||||||
device does not support ageing, the driver can simulate ageing using a
|
device does not support ageing, the driver can simulate ageing using a
|
||||||
garbage collection timer to monitor FBD entries. Expired entries will be
|
garbage collection timer to monitor FDB entries. Expired entries will be
|
||||||
notified to the bridge using SWITCHDEV_FDB_DEL. See rocker driver for
|
notified to the bridge using SWITCHDEV_FDB_DEL. See rocker driver for
|
||||||
example of driver running ageing timer.
|
example of driver running ageing timer.
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -435,7 +435,8 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
|
||||||
PM status to 'suspended' and update its parent's counter of 'active'
|
PM status to 'suspended' and update its parent's counter of 'active'
|
||||||
children as appropriate (it is only valid to use this function if
|
children as appropriate (it is only valid to use this function if
|
||||||
'power.runtime_error' is set or 'power.disable_depth' is greater than
|
'power.runtime_error' is set or 'power.disable_depth' is greater than
|
||||||
zero)
|
zero); it will fail and return an error code if the device has a child
|
||||||
|
which is active and the 'power.ignore_children' flag is unset
|
||||||
|
|
||||||
bool pm_runtime_active(struct device *dev);
|
bool pm_runtime_active(struct device *dev);
|
||||||
- return true if the device's runtime PM status is 'active' or its
|
- return true if the device's runtime PM status is 'active' or its
|
||||||
|
|
|
||||||
|
|
@ -58,20 +58,23 @@ Symbols/Function Pointers
|
||||||
%ps versatile_init
|
%ps versatile_init
|
||||||
%pB prev_fn_of_versatile_init+0x88/0x88
|
%pB prev_fn_of_versatile_init+0x88/0x88
|
||||||
|
|
||||||
For printing symbols and function pointers. The ``S`` and ``s`` specifiers
|
The ``F`` and ``f`` specifiers are for printing function pointers,
|
||||||
result in the symbol name with (``S``) or without (``s``) offsets. Where
|
for example, f->func, &gettimeofday. They have the same result as
|
||||||
this is used on a kernel without KALLSYMS - the symbol address is
|
``S`` and ``s`` specifiers. But they do an extra conversion on
|
||||||
printed instead.
|
ia64, ppc64 and parisc64 architectures where the function pointers
|
||||||
|
are actually function descriptors.
|
||||||
|
|
||||||
|
The ``S`` and ``s`` specifiers can be used for printing symbols
|
||||||
|
from direct addresses, for example, __builtin_return_address(0),
|
||||||
|
(void *)regs->ip. They result in the symbol name with (``S``) or
|
||||||
|
without (``s``) offsets. If KALLSYMS are disabled then the symbol
|
||||||
|
address is printed instead.
|
||||||
|
|
||||||
The ``B`` specifier results in the symbol name with offsets and should be
|
The ``B`` specifier results in the symbol name with offsets and should be
|
||||||
used when printing stack backtraces. The specifier takes into
|
used when printing stack backtraces. The specifier takes into
|
||||||
consideration the effect of compiler optimisations which may occur
|
consideration the effect of compiler optimisations which may occur
|
||||||
when tail-call``s are used and marked with the noreturn GCC attribute.
|
when tail-call``s are used and marked with the noreturn GCC attribute.
|
||||||
|
|
||||||
On ia64, ppc64 and parisc64 architectures function pointers are
|
|
||||||
actually function descriptors which must first be resolved. The ``F`` and
|
|
||||||
``f`` specifiers perform this resolution and then provide the same
|
|
||||||
functionality as the ``S`` and ``s`` specifiers.
|
|
||||||
|
|
||||||
Kernel Pointers
|
Kernel Pointers
|
||||||
===============
|
===============
|
||||||
|
|
|
||||||
|
|
@ -35,9 +35,34 @@ Table : Subdirectories in /proc/sys/net
|
||||||
bpf_jit_enable
|
bpf_jit_enable
|
||||||
--------------
|
--------------
|
||||||
|
|
||||||
This enables Berkeley Packet Filter Just in Time compiler.
|
This enables the BPF Just in Time (JIT) compiler. BPF is a flexible
|
||||||
Currently supported on x86_64 architecture, bpf_jit provides a framework
|
and efficient infrastructure allowing to execute bytecode at various
|
||||||
to speed packet filtering, the one used by tcpdump/libpcap for example.
|
hook points. It is used in a number of Linux kernel subsystems such
|
||||||
|
as networking (e.g. XDP, tc), tracing (e.g. kprobes, uprobes, tracepoints)
|
||||||
|
and security (e.g. seccomp). LLVM has a BPF back end that can compile
|
||||||
|
restricted C into a sequence of BPF instructions. After program load
|
||||||
|
through bpf(2) and passing a verifier in the kernel, a JIT will then
|
||||||
|
translate these BPF proglets into native CPU instructions. There are
|
||||||
|
two flavors of JITs, the newer eBPF JIT currently supported on:
|
||||||
|
- x86_64
|
||||||
|
- arm64
|
||||||
|
- ppc64
|
||||||
|
- sparc64
|
||||||
|
- mips64
|
||||||
|
- s390x
|
||||||
|
|
||||||
|
And the older cBPF JIT supported on the following archs:
|
||||||
|
- arm
|
||||||
|
- mips
|
||||||
|
- ppc
|
||||||
|
- sparc
|
||||||
|
|
||||||
|
eBPF JITs are a superset of cBPF JITs, meaning the kernel will
|
||||||
|
migrate cBPF instructions into eBPF instructions and then JIT
|
||||||
|
compile them transparently. Older cBPF JITs can only translate
|
||||||
|
tcpdump filters, seccomp rules, etc, but not mentioned eBPF
|
||||||
|
programs loaded through bpf(2).
|
||||||
|
|
||||||
Values :
|
Values :
|
||||||
0 - disable the JIT (default value)
|
0 - disable the JIT (default value)
|
||||||
1 - enable the JIT
|
1 - enable the JIT
|
||||||
|
|
@ -46,9 +71,9 @@ Values :
|
||||||
bpf_jit_harden
|
bpf_jit_harden
|
||||||
--------------
|
--------------
|
||||||
|
|
||||||
This enables hardening for the Berkeley Packet Filter Just in Time compiler.
|
This enables hardening for the BPF JIT compiler. Supported are eBPF
|
||||||
Supported are eBPF JIT backends. Enabling hardening trades off performance,
|
JIT backends. Enabling hardening trades off performance, but can
|
||||||
but can mitigate JIT spraying.
|
mitigate JIT spraying.
|
||||||
Values :
|
Values :
|
||||||
0 - disable JIT hardening (default value)
|
0 - disable JIT hardening (default value)
|
||||||
1 - enable JIT hardening for unprivileged users only
|
1 - enable JIT hardening for unprivileged users only
|
||||||
|
|
@ -57,11 +82,11 @@ Values :
|
||||||
bpf_jit_kallsyms
|
bpf_jit_kallsyms
|
||||||
----------------
|
----------------
|
||||||
|
|
||||||
When Berkeley Packet Filter Just in Time compiler is enabled, then compiled
|
When BPF JIT compiler is enabled, then compiled images are unknown
|
||||||
images are unknown addresses to the kernel, meaning they neither show up in
|
addresses to the kernel, meaning they neither show up in traces nor
|
||||||
traces nor in /proc/kallsyms. This enables export of these addresses, which
|
in /proc/kallsyms. This enables export of these addresses, which can
|
||||||
can be used for debugging/tracing. If bpf_jit_harden is enabled, this feature
|
be used for debugging/tracing. If bpf_jit_harden is enabled, this
|
||||||
is disabled.
|
feature is disabled.
|
||||||
Values :
|
Values :
|
||||||
0 - disable JIT kallsyms export (default value)
|
0 - disable JIT kallsyms export (default value)
|
||||||
1 - enable JIT kallsyms export for privileged users only
|
1 - enable JIT kallsyms export for privileged users only
|
||||||
|
|
|
||||||
5076
MAINTAINERS
5076
MAINTAINERS
File diff suppressed because it is too large
Load diff
11
Makefile
11
Makefile
|
|
@ -1,7 +1,7 @@
|
||||||
VERSION = 4
|
VERSION = 4
|
||||||
PATCHLEVEL = 13
|
PATCHLEVEL = 13
|
||||||
SUBLEVEL = 0
|
SUBLEVEL = 0
|
||||||
EXTRAVERSION = -rc1
|
EXTRAVERSION =
|
||||||
NAME = Fearless Coyote
|
NAME = Fearless Coyote
|
||||||
|
|
||||||
# *DOCUMENTATION*
|
# *DOCUMENTATION*
|
||||||
|
|
@ -396,7 +396,7 @@ LINUXINCLUDE := \
|
||||||
KBUILD_CPPFLAGS := -D__KERNEL__
|
KBUILD_CPPFLAGS := -D__KERNEL__
|
||||||
|
|
||||||
KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
|
KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
|
||||||
-fno-strict-aliasing -fno-common \
|
-fno-strict-aliasing -fno-common -fshort-wchar \
|
||||||
-Werror-implicit-function-declaration \
|
-Werror-implicit-function-declaration \
|
||||||
-Wno-format-security \
|
-Wno-format-security \
|
||||||
-std=gnu89 $(call cc-option,-fno-PIE)
|
-std=gnu89 $(call cc-option,-fno-PIE)
|
||||||
|
|
@ -442,7 +442,7 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
|
||||||
# ===========================================================================
|
# ===========================================================================
|
||||||
# Rules shared between *config targets and build targets
|
# Rules shared between *config targets and build targets
|
||||||
|
|
||||||
# Basic helpers built in scripts/
|
# Basic helpers built in scripts/basic/
|
||||||
PHONY += scripts_basic
|
PHONY += scripts_basic
|
||||||
scripts_basic:
|
scripts_basic:
|
||||||
$(Q)$(MAKE) $(build)=scripts/basic
|
$(Q)$(MAKE) $(build)=scripts/basic
|
||||||
|
|
@ -505,7 +505,7 @@ ifeq ($(KBUILD_EXTMOD),)
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
# install and module_install need also be processed one by one
|
# install and modules_install need also be processed one by one
|
||||||
ifneq ($(filter install,$(MAKECMDGOALS)),)
|
ifneq ($(filter install,$(MAKECMDGOALS)),)
|
||||||
ifneq ($(filter modules_install,$(MAKECMDGOALS)),)
|
ifneq ($(filter modules_install,$(MAKECMDGOALS)),)
|
||||||
mixed-targets := 1
|
mixed-targets := 1
|
||||||
|
|
@ -964,7 +964,7 @@ export KBUILD_VMLINUX_MAIN := $(core-y) $(libs-y2) $(drivers-y) $(net-y) $(virt-
|
||||||
export KBUILD_VMLINUX_LIBS := $(libs-y1)
|
export KBUILD_VMLINUX_LIBS := $(libs-y1)
|
||||||
export KBUILD_LDS := arch/$(SRCARCH)/kernel/vmlinux.lds
|
export KBUILD_LDS := arch/$(SRCARCH)/kernel/vmlinux.lds
|
||||||
export LDFLAGS_vmlinux
|
export LDFLAGS_vmlinux
|
||||||
# used by scripts/pacmage/Makefile
|
# used by scripts/package/Makefile
|
||||||
export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) arch Documentation include samples scripts tools)
|
export KBUILD_ALLDIRS := $(sort $(filter-out arch/%,$(vmlinux-alldirs)) arch Documentation include samples scripts tools)
|
||||||
|
|
||||||
vmlinux-deps := $(KBUILD_LDS) $(KBUILD_VMLINUX_INIT) $(KBUILD_VMLINUX_MAIN) $(KBUILD_VMLINUX_LIBS)
|
vmlinux-deps := $(KBUILD_LDS) $(KBUILD_VMLINUX_INIT) $(KBUILD_VMLINUX_MAIN) $(KBUILD_VMLINUX_LIBS)
|
||||||
|
|
@ -1184,6 +1184,7 @@ PHONY += kselftest
|
||||||
kselftest:
|
kselftest:
|
||||||
$(Q)$(MAKE) -C tools/testing/selftests run_tests
|
$(Q)$(MAKE) -C tools/testing/selftests run_tests
|
||||||
|
|
||||||
|
PHONY += kselftest-clean
|
||||||
kselftest-clean:
|
kselftest-clean:
|
||||||
$(Q)$(MAKE) -C tools/testing/selftests clean
|
$(Q)$(MAKE) -C tools/testing/selftests clean
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -299,6 +299,7 @@ static inline void __iomem * ioremap_nocache(unsigned long offset,
|
||||||
return ioremap(offset, size);
|
return ioremap(offset, size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define ioremap_wc ioremap_nocache
|
||||||
#define ioremap_uc ioremap_nocache
|
#define ioremap_uc ioremap_nocache
|
||||||
|
|
||||||
static inline void iounmap(volatile void __iomem *addr)
|
static inline void iounmap(volatile void __iomem *addr)
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
#ifndef _ALPHA_TYPES_H
|
#ifndef _ALPHA_TYPES_H
|
||||||
#define _ALPHA_TYPES_H
|
#define _ALPHA_TYPES_H
|
||||||
|
|
||||||
#include <asm-generic/int-ll64.h>
|
#include <uapi/asm/types.h>
|
||||||
|
|
||||||
#endif /* _ALPHA_TYPES_H */
|
#endif /* _ALPHA_TYPES_H */
|
||||||
|
|
|
||||||
|
|
@ -3,7 +3,7 @@
|
||||||
|
|
||||||
#include <uapi/asm/unistd.h>
|
#include <uapi/asm/unistd.h>
|
||||||
|
|
||||||
#define NR_SYSCALLS 514
|
#define NR_SYSCALLS 523
|
||||||
|
|
||||||
#define __ARCH_WANT_OLD_READDIR
|
#define __ARCH_WANT_OLD_READDIR
|
||||||
#define __ARCH_WANT_STAT64
|
#define __ARCH_WANT_STAT64
|
||||||
|
|
|
||||||
|
|
@ -100,7 +100,7 @@
|
||||||
#define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */
|
#define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */
|
||||||
#define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */
|
#define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */
|
||||||
#define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */
|
#define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */
|
||||||
#define TIOCGPTPEER _IOR('T', 0x41, int) /* Safely open the slave */
|
#define TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */
|
||||||
|
|
||||||
#define TIOCSERCONFIG 0x5453
|
#define TIOCSERCONFIG 0x5453
|
||||||
#define TIOCSERGWILD 0x5454
|
#define TIOCSERGWILD 0x5454
|
||||||
|
|
|
||||||
|
|
@ -9,8 +9,18 @@
|
||||||
* need to be careful to avoid a name clashes.
|
* need to be careful to avoid a name clashes.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __KERNEL__
|
/*
|
||||||
|
* This is here because we used to use l64 for alpha
|
||||||
|
* and we don't want to impact user mode with our change to ll64
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* However, some user programs are fine with this. They can
|
||||||
|
* flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
|
||||||
|
*/
|
||||||
|
#if !defined(__SANE_USERSPACE_TYPES__) && !defined(__KERNEL__)
|
||||||
#include <asm-generic/int-l64.h>
|
#include <asm-generic/int-l64.h>
|
||||||
|
#else
|
||||||
|
#include <asm-generic/int-ll64.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* _UAPI_ALPHA_TYPES_H */
|
#endif /* _UAPI_ALPHA_TYPES_H */
|
||||||
|
|
|
||||||
|
|
@ -475,5 +475,19 @@
|
||||||
#define __NR_getrandom 511
|
#define __NR_getrandom 511
|
||||||
#define __NR_memfd_create 512
|
#define __NR_memfd_create 512
|
||||||
#define __NR_execveat 513
|
#define __NR_execveat 513
|
||||||
|
#define __NR_seccomp 514
|
||||||
|
#define __NR_bpf 515
|
||||||
|
#define __NR_userfaultfd 516
|
||||||
|
#define __NR_membarrier 517
|
||||||
|
#define __NR_mlock2 518
|
||||||
|
#define __NR_copy_file_range 519
|
||||||
|
#define __NR_preadv2 520
|
||||||
|
#define __NR_pwritev2 521
|
||||||
|
#define __NR_statx 522
|
||||||
|
|
||||||
|
/* Alpha doesn't have protection keys. */
|
||||||
|
#define __IGNORE_pkey_mprotect
|
||||||
|
#define __IGNORE_pkey_alloc
|
||||||
|
#define __IGNORE_pkey_free
|
||||||
|
|
||||||
#endif /* _UAPI_ALPHA_UNISTD_H */
|
#endif /* _UAPI_ALPHA_UNISTD_H */
|
||||||
|
|
|
||||||
|
|
@ -351,7 +351,7 @@ marvel_init_io7(struct io7 *io7)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void __init
|
||||||
marvel_io7_present(gct6_node *node)
|
marvel_io7_present(gct6_node *node)
|
||||||
{
|
{
|
||||||
int pe;
|
int pe;
|
||||||
|
|
@ -369,6 +369,7 @@ marvel_io7_present(gct6_node *node)
|
||||||
static void __init
|
static void __init
|
||||||
marvel_find_console_vga_hose(void)
|
marvel_find_console_vga_hose(void)
|
||||||
{
|
{
|
||||||
|
#ifdef CONFIG_VGA_HOSE
|
||||||
u64 *pu64 = (u64 *)((u64)hwrpb + hwrpb->ctbt_offset);
|
u64 *pu64 = (u64 *)((u64)hwrpb + hwrpb->ctbt_offset);
|
||||||
|
|
||||||
if (pu64[7] == 3) { /* TERM_TYPE == graphics */
|
if (pu64[7] == 3) { /* TERM_TYPE == graphics */
|
||||||
|
|
@ -402,9 +403,10 @@ marvel_find_console_vga_hose(void)
|
||||||
pci_vga_hose = hose;
|
pci_vga_hose = hose;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
gct6_search_struct gct_wanted_node_list[] = {
|
gct6_search_struct gct_wanted_node_list[] __initdata = {
|
||||||
{ GCT_TYPE_HOSE, GCT_SUBTYPE_IO_PORT_MODULE, marvel_io7_present },
|
{ GCT_TYPE_HOSE, GCT_SUBTYPE_IO_PORT_MODULE, marvel_io7_present },
|
||||||
{ 0, 0, NULL }
|
{ 0, 0, NULL }
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -461,6 +461,7 @@ titan_ioremap(unsigned long addr, unsigned long size)
|
||||||
unsigned long *ptes;
|
unsigned long *ptes;
|
||||||
unsigned long pfn;
|
unsigned long pfn;
|
||||||
|
|
||||||
|
#ifdef CONFIG_VGA_HOSE
|
||||||
/*
|
/*
|
||||||
* Adjust the address and hose, if necessary.
|
* Adjust the address and hose, if necessary.
|
||||||
*/
|
*/
|
||||||
|
|
@ -468,6 +469,7 @@ titan_ioremap(unsigned long addr, unsigned long size)
|
||||||
h = pci_vga_hose->index;
|
h = pci_vga_hose->index;
|
||||||
addr += pci_vga_hose->mem_space->start;
|
addr += pci_vga_hose->mem_space->start;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Find the hose.
|
* Find the hose.
|
||||||
|
|
|
||||||
|
|
@ -181,6 +181,9 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab,
|
||||||
switch (r_type) {
|
switch (r_type) {
|
||||||
case R_ALPHA_NONE:
|
case R_ALPHA_NONE:
|
||||||
break;
|
break;
|
||||||
|
case R_ALPHA_REFLONG:
|
||||||
|
*(u32 *)location = value;
|
||||||
|
break;
|
||||||
case R_ALPHA_REFQUAD:
|
case R_ALPHA_REFQUAD:
|
||||||
/* BUG() can produce misaligned relocations. */
|
/* BUG() can produce misaligned relocations. */
|
||||||
((u32 *)location)[0] = value;
|
((u32 *)location)[0] = value;
|
||||||
|
|
|
||||||
|
|
@ -115,7 +115,7 @@ wait_boot_cpu_to_stop(int cpuid)
|
||||||
/*
|
/*
|
||||||
* Where secondaries begin a life of C.
|
* Where secondaries begin a life of C.
|
||||||
*/
|
*/
|
||||||
void
|
void __init
|
||||||
smp_callin(void)
|
smp_callin(void)
|
||||||
{
|
{
|
||||||
int cpuid = hard_smp_processor_id();
|
int cpuid = hard_smp_processor_id();
|
||||||
|
|
|
||||||
|
|
@ -532,6 +532,15 @@ sys_call_table:
|
||||||
.quad sys_getrandom
|
.quad sys_getrandom
|
||||||
.quad sys_memfd_create
|
.quad sys_memfd_create
|
||||||
.quad sys_execveat
|
.quad sys_execveat
|
||||||
|
.quad sys_seccomp
|
||||||
|
.quad sys_bpf /* 515 */
|
||||||
|
.quad sys_userfaultfd
|
||||||
|
.quad sys_membarrier
|
||||||
|
.quad sys_mlock2
|
||||||
|
.quad sys_copy_file_range
|
||||||
|
.quad sys_preadv2 /* 520 */
|
||||||
|
.quad sys_pwritev2
|
||||||
|
.quad sys_statx
|
||||||
|
|
||||||
.size sys_call_table, . - sys_call_table
|
.size sys_call_table, . - sys_call_table
|
||||||
.type sys_call_table, @object
|
.type sys_call_table, @object
|
||||||
|
|
|
||||||
|
|
@ -20,12 +20,8 @@ lib-y = __divqu.o __remqu.o __divlu.o __remlu.o \
|
||||||
checksum.o \
|
checksum.o \
|
||||||
csum_partial_copy.o \
|
csum_partial_copy.o \
|
||||||
$(ev67-y)strlen.o \
|
$(ev67-y)strlen.o \
|
||||||
$(ev67-y)strcat.o \
|
stycpy.o \
|
||||||
strcpy.o \
|
styncpy.o \
|
||||||
$(ev67-y)strncat.o \
|
|
||||||
strncpy.o \
|
|
||||||
$(ev6-y)stxcpy.o \
|
|
||||||
$(ev6-y)stxncpy.o \
|
|
||||||
$(ev67-y)strchr.o \
|
$(ev67-y)strchr.o \
|
||||||
$(ev67-y)strrchr.o \
|
$(ev67-y)strrchr.o \
|
||||||
$(ev6-y)memchr.o \
|
$(ev6-y)memchr.o \
|
||||||
|
|
@ -49,3 +45,17 @@ AFLAGS___remlu.o = -DREM -DINTSIZE
|
||||||
$(addprefix $(obj)/,__divqu.o __remqu.o __divlu.o __remlu.o): \
|
$(addprefix $(obj)/,__divqu.o __remqu.o __divlu.o __remlu.o): \
|
||||||
$(src)/$(ev6-y)divide.S FORCE
|
$(src)/$(ev6-y)divide.S FORCE
|
||||||
$(call if_changed_rule,as_o_S)
|
$(call if_changed_rule,as_o_S)
|
||||||
|
|
||||||
|
# There are direct branches between {str*cpy,str*cat} and stx*cpy.
|
||||||
|
# Ensure the branches are within range by merging these objects.
|
||||||
|
|
||||||
|
LDFLAGS_stycpy.o := -r
|
||||||
|
LDFLAGS_styncpy.o := -r
|
||||||
|
|
||||||
|
$(obj)/stycpy.o: $(obj)/strcpy.o $(obj)/$(ev67-y)strcat.o \
|
||||||
|
$(obj)/$(ev6-y)stxcpy.o FORCE
|
||||||
|
$(call if_changed,ld)
|
||||||
|
|
||||||
|
$(obj)/styncpy.o: $(obj)/strncpy.o $(obj)/$(ev67-y)strncat.o \
|
||||||
|
$(obj)/$(ev6-y)stxncpy.o FORCE
|
||||||
|
$(call if_changed,ld)
|
||||||
|
|
|
||||||
|
|
@ -34,7 +34,7 @@
|
||||||
.ent __copy_user
|
.ent __copy_user
|
||||||
__copy_user:
|
__copy_user:
|
||||||
.prologue 0
|
.prologue 0
|
||||||
and $18,$18,$0
|
mov $18,$0
|
||||||
and $16,7,$3
|
and $16,7,$3
|
||||||
beq $0,$35
|
beq $0,$35
|
||||||
beq $3,$36
|
beq $3,$36
|
||||||
|
|
|
||||||
|
|
@ -45,9 +45,10 @@
|
||||||
# Pipeline info: Slotting & Comments
|
# Pipeline info: Slotting & Comments
|
||||||
__copy_user:
|
__copy_user:
|
||||||
.prologue 0
|
.prologue 0
|
||||||
andq $18, $18, $0
|
mov $18, $0 # .. .. .. E
|
||||||
subq $18, 32, $1 # .. E .. .. : Is this going to be a small copy?
|
subq $18, 32, $1 # .. .. E. .. : Is this going to be a small copy?
|
||||||
beq $0, $zerolength # U .. .. .. : U L U L
|
nop # .. E .. ..
|
||||||
|
beq $18, $zerolength # U .. .. .. : U L U L
|
||||||
|
|
||||||
and $16,7,$3 # .. .. .. E : is leading dest misalignment
|
and $16,7,$3 # .. .. .. E : is leading dest misalignment
|
||||||
ble $1, $onebyteloop # .. .. U .. : 1st branch : small amount of data
|
ble $1, $onebyteloop # .. .. U .. : 1st branch : small amount of data
|
||||||
|
|
|
||||||
|
|
@ -96,7 +96,6 @@ menu "ARC Architecture Configuration"
|
||||||
|
|
||||||
menu "ARC Platform/SoC/Board"
|
menu "ARC Platform/SoC/Board"
|
||||||
|
|
||||||
source "arch/arc/plat-sim/Kconfig"
|
|
||||||
source "arch/arc/plat-tb10x/Kconfig"
|
source "arch/arc/plat-tb10x/Kconfig"
|
||||||
source "arch/arc/plat-axs10x/Kconfig"
|
source "arch/arc/plat-axs10x/Kconfig"
|
||||||
#New platform adds here
|
#New platform adds here
|
||||||
|
|
|
||||||
|
|
@ -107,7 +107,7 @@ core-y += arch/arc/
|
||||||
# w/o this dtb won't embed into kernel binary
|
# w/o this dtb won't embed into kernel binary
|
||||||
core-y += arch/arc/boot/dts/
|
core-y += arch/arc/boot/dts/
|
||||||
|
|
||||||
core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/
|
core-y += arch/arc/plat-sim/
|
||||||
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
|
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
|
||||||
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
|
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
|
||||||
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
|
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
|
||||||
|
|
|
||||||
|
|
@ -15,15 +15,15 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "snps,arc";
|
compatible = "snps,arc";
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
cpu_card {
|
cpu_card {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
ranges = <0x00000000 0xf0000000 0x10000000>;
|
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
|
||||||
|
|
||||||
core_clk: core_clk {
|
core_clk: core_clk {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
|
|
@ -91,23 +91,21 @@
|
||||||
mb_intc: dw-apb-ictl@0xe0012000 {
|
mb_intc: dw-apb-ictl@0xe0012000 {
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
compatible = "snps,dw-apb-ictl";
|
compatible = "snps,dw-apb-ictl";
|
||||||
reg = < 0xe0012000 0x200 >;
|
reg = < 0x0 0xe0012000 0x0 0x200 >;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
interrupt-parent = <&core_intc>;
|
interrupt-parent = <&core_intc>;
|
||||||
interrupts = < 7 >;
|
interrupts = < 7 >;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0x00000000 0x80000000 0x20000000>;
|
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */
|
/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
|
||||||
|
reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
|
||||||
};
|
};
|
||||||
|
|
||||||
reserved-memory {
|
reserved-memory {
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
/*
|
/*
|
||||||
* We just move frame buffer area to the very end of
|
* We just move frame buffer area to the very end of
|
||||||
|
|
@ -118,7 +116,7 @@
|
||||||
*/
|
*/
|
||||||
frame_buffer: frame_buffer@9e000000 {
|
frame_buffer: frame_buffer@9e000000 {
|
||||||
compatible = "shared-dma-pool";
|
compatible = "shared-dma-pool";
|
||||||
reg = <0x9e000000 0x2000000>;
|
reg = <0x0 0x9e000000 0x0 0x2000000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -14,15 +14,15 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "snps,arc";
|
compatible = "snps,arc";
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
cpu_card {
|
cpu_card {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
ranges = <0x00000000 0xf0000000 0x10000000>;
|
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
|
||||||
|
|
||||||
core_clk: core_clk {
|
core_clk: core_clk {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
|
|
@ -94,30 +94,29 @@
|
||||||
mb_intc: dw-apb-ictl@0xe0012000 {
|
mb_intc: dw-apb-ictl@0xe0012000 {
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
compatible = "snps,dw-apb-ictl";
|
compatible = "snps,dw-apb-ictl";
|
||||||
reg = < 0xe0012000 0x200 >;
|
reg = < 0x0 0xe0012000 0x0 0x200 >;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
interrupt-parent = <&core_intc>;
|
interrupt-parent = <&core_intc>;
|
||||||
interrupts = < 24 >;
|
interrupts = < 24 >;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0x00000000 0x80000000 0x40000000>;
|
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
|
||||||
|
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
|
||||||
|
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
|
||||||
};
|
};
|
||||||
|
|
||||||
reserved-memory {
|
reserved-memory {
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
/*
|
/*
|
||||||
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
||||||
*/
|
*/
|
||||||
frame_buffer: frame_buffer@be000000 {
|
frame_buffer: frame_buffer@be000000 {
|
||||||
compatible = "shared-dma-pool";
|
compatible = "shared-dma-pool";
|
||||||
reg = <0xbe000000 0x2000000>;
|
reg = <0x0 0xbe000000 0x0 0x2000000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -14,15 +14,15 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "snps,arc";
|
compatible = "snps,arc";
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
|
|
||||||
cpu_card {
|
cpu_card {
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
ranges = <0x00000000 0xf0000000 0x10000000>;
|
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
|
||||||
|
|
||||||
core_clk: core_clk {
|
core_clk: core_clk {
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
|
|
@ -100,30 +100,29 @@
|
||||||
mb_intc: dw-apb-ictl@0xe0012000 {
|
mb_intc: dw-apb-ictl@0xe0012000 {
|
||||||
#interrupt-cells = <1>;
|
#interrupt-cells = <1>;
|
||||||
compatible = "snps,dw-apb-ictl";
|
compatible = "snps,dw-apb-ictl";
|
||||||
reg = < 0xe0012000 0x200 >;
|
reg = < 0x0 0xe0012000 0x0 0x200 >;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
interrupt-parent = <&idu_intc>;
|
interrupt-parent = <&idu_intc>;
|
||||||
interrupts = <0>;
|
interrupts = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0x00000000 0x80000000 0x40000000>;
|
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x80000000 0x20000000>; /* 512MiB */
|
/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
|
||||||
|
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
|
||||||
|
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
|
||||||
};
|
};
|
||||||
|
|
||||||
reserved-memory {
|
reserved-memory {
|
||||||
#address-cells = <1>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
/*
|
/*
|
||||||
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
* Move frame buffer out of IOC aperture (0x8z-0xAz).
|
||||||
*/
|
*/
|
||||||
frame_buffer: frame_buffer@be000000 {
|
frame_buffer: frame_buffer@be000000 {
|
||||||
compatible = "shared-dma-pool";
|
compatible = "shared-dma-pool";
|
||||||
reg = <0xbe000000 0x2000000>;
|
reg = <0x0 0xbe000000 0x0 0x2000000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -13,7 +13,7 @@
|
||||||
compatible = "simple-bus";
|
compatible = "simple-bus";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges = <0x00000000 0xe0000000 0x10000000>;
|
ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
|
||||||
interrupt-parent = <&mb_intc>;
|
interrupt-parent = <&mb_intc>;
|
||||||
|
|
||||||
i2sclk: i2sclk@100a0 {
|
i2sclk: i2sclk@100a0 {
|
||||||
|
|
|
||||||
|
|
@ -21,7 +21,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs"
|
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs"
|
||||||
CONFIG_PREEMPT=y
|
CONFIG_PREEMPT=y
|
||||||
|
|
|
||||||
|
|
@ -23,7 +23,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_SMP=y
|
CONFIG_SMP=y
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu"
|
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu"
|
||||||
|
|
|
||||||
|
|
@ -39,7 +39,6 @@ CONFIG_IP_PNP=y
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||||
# CONFIG_INET_LRO is not set
|
|
||||||
# CONFIG_INET_DIAG is not set
|
# CONFIG_INET_DIAG is not set
|
||||||
# CONFIG_IPV6 is not set
|
# CONFIG_IPV6 is not set
|
||||||
# CONFIG_WIRELESS is not set
|
# CONFIG_WIRELESS is not set
|
||||||
|
|
|
||||||
|
|
@ -23,7 +23,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700"
|
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700"
|
||||||
CONFIG_PREEMPT=y
|
CONFIG_PREEMPT=y
|
||||||
# CONFIG_COMPACTION is not set
|
# CONFIG_COMPACTION is not set
|
||||||
|
|
|
||||||
|
|
@ -26,7 +26,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs"
|
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs"
|
||||||
CONFIG_PREEMPT=y
|
CONFIG_PREEMPT=y
|
||||||
|
|
|
||||||
|
|
@ -24,7 +24,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_SMP=y
|
CONFIG_SMP=y
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu"
|
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu"
|
||||||
|
|
|
||||||
|
|
@ -23,7 +23,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
|
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
|
||||||
# CONFIG_COMPACTION is not set
|
# CONFIG_COMPACTION is not set
|
||||||
CONFIG_NET=y
|
CONFIG_NET=y
|
||||||
|
|
|
||||||
|
|
@ -23,7 +23,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
|
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
|
||||||
# CONFIG_COMPACTION is not set
|
# CONFIG_COMPACTION is not set
|
||||||
|
|
|
||||||
|
|
@ -18,7 +18,6 @@ CONFIG_MODULES=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
# CONFIG_IOSCHED_DEADLINE is not set
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
CONFIG_ARC_PLAT_SIM=y
|
|
||||||
CONFIG_ISA_ARCV2=y
|
CONFIG_ISA_ARCV2=y
|
||||||
CONFIG_SMP=y
|
CONFIG_SMP=y
|
||||||
# CONFIG_ARC_TIMERS_64BIT is not set
|
# CONFIG_ARC_TIMERS_64BIT is not set
|
||||||
|
|
|
||||||
|
|
@ -38,7 +38,6 @@ CONFIG_IP_MULTICAST=y
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||||
# CONFIG_INET_LRO is not set
|
|
||||||
# CONFIG_INET_DIAG is not set
|
# CONFIG_INET_DIAG is not set
|
||||||
# CONFIG_IPV6 is not set
|
# CONFIG_IPV6 is not set
|
||||||
# CONFIG_WIRELESS is not set
|
# CONFIG_WIRELESS is not set
|
||||||
|
|
|
||||||
|
|
@ -96,7 +96,9 @@ extern unsigned long perip_base, perip_end;
|
||||||
#define ARC_REG_SLC_FLUSH 0x904
|
#define ARC_REG_SLC_FLUSH 0x904
|
||||||
#define ARC_REG_SLC_INVALIDATE 0x905
|
#define ARC_REG_SLC_INVALIDATE 0x905
|
||||||
#define ARC_REG_SLC_RGN_START 0x914
|
#define ARC_REG_SLC_RGN_START 0x914
|
||||||
|
#define ARC_REG_SLC_RGN_START1 0x915
|
||||||
#define ARC_REG_SLC_RGN_END 0x916
|
#define ARC_REG_SLC_RGN_END 0x916
|
||||||
|
#define ARC_REG_SLC_RGN_END1 0x917
|
||||||
|
|
||||||
/* Bit val in SLC_CONTROL */
|
/* Bit val in SLC_CONTROL */
|
||||||
#define SLC_CTRL_DIS 0x001
|
#define SLC_CTRL_DIS 0x001
|
||||||
|
|
|
||||||
|
|
@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void)
|
||||||
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
|
return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
extern int pae40_exist_but_not_enab(void);
|
||||||
|
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -75,10 +75,20 @@ void arc_init_IRQ(void)
|
||||||
* Set a default priority for all available interrupts to prevent
|
* Set a default priority for all available interrupts to prevent
|
||||||
* switching of register banks if Fast IRQ and multiple register banks
|
* switching of register banks if Fast IRQ and multiple register banks
|
||||||
* are supported by CPU.
|
* are supported by CPU.
|
||||||
|
* Also disable private-per-core IRQ lines so faulty external HW won't
|
||||||
|
* trigger interrupt that kernel is not ready to handle.
|
||||||
*/
|
*/
|
||||||
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
|
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
|
||||||
write_aux_reg(AUX_IRQ_SELECT, i);
|
write_aux_reg(AUX_IRQ_SELECT, i);
|
||||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Only mask cpu private IRQs here.
|
||||||
|
* "common" interrupts are masked at IDU, otherwise it would
|
||||||
|
* need to be unmasked at each cpu, with IPIs
|
||||||
|
*/
|
||||||
|
if (i < FIRST_EXT_IRQ)
|
||||||
|
write_aux_reg(AUX_IRQ_ENABLE, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||||
|
|
|
||||||
|
|
@ -27,7 +27,7 @@
|
||||||
*/
|
*/
|
||||||
void arc_init_IRQ(void)
|
void arc_init_IRQ(void)
|
||||||
{
|
{
|
||||||
int level_mask = 0;
|
unsigned int level_mask = 0, i;
|
||||||
|
|
||||||
/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
|
/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
|
||||||
level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
|
level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
|
||||||
|
|
@ -40,6 +40,18 @@ void arc_init_IRQ(void)
|
||||||
|
|
||||||
if (level_mask)
|
if (level_mask)
|
||||||
pr_info("Level-2 interrupts bitset %x\n", level_mask);
|
pr_info("Level-2 interrupts bitset %x\n", level_mask);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable all IRQ lines so faulty external hardware won't
|
||||||
|
* trigger interrupt that kernel is not ready to handle.
|
||||||
|
*/
|
||||||
|
for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
|
||||||
|
unsigned int ienb;
|
||||||
|
|
||||||
|
ienb = read_aux_reg(AUX_IENABLE);
|
||||||
|
ienb &= ~(1 << i);
|
||||||
|
write_aux_reg(AUX_IENABLE, ienb);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -665,6 +665,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
|
||||||
static DEFINE_SPINLOCK(lock);
|
static DEFINE_SPINLOCK(lock);
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned int ctrl;
|
unsigned int ctrl;
|
||||||
|
phys_addr_t end;
|
||||||
|
|
||||||
spin_lock_irqsave(&lock, flags);
|
spin_lock_irqsave(&lock, flags);
|
||||||
|
|
||||||
|
|
@ -694,8 +695,19 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
|
||||||
* END needs to be setup before START (latter triggers the operation)
|
* END needs to be setup before START (latter triggers the operation)
|
||||||
* END can't be same as START, so add (l2_line_sz - 1) to sz
|
* END can't be same as START, so add (l2_line_sz - 1) to sz
|
||||||
*/
|
*/
|
||||||
write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
|
end = paddr + sz + l2_line_sz - 1;
|
||||||
write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
|
if (is_pae40_enabled())
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
|
||||||
|
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
|
||||||
|
|
||||||
|
if (is_pae40_enabled())
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
|
||||||
|
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
|
||||||
|
|
||||||
|
/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
|
||||||
|
read_aux_reg(ARC_REG_SLC_CTRL);
|
||||||
|
|
||||||
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
|
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
|
||||||
|
|
||||||
|
|
@ -1111,6 +1123,13 @@ noinline void __init arc_ioc_setup(void)
|
||||||
__dc_enable();
|
__dc_enable();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Cache related boot time checks/setups only needed on master CPU:
|
||||||
|
* - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES)
|
||||||
|
* Assume SMP only, so all cores will have same cache config. A check on
|
||||||
|
* one core suffices for all
|
||||||
|
* - IOC setup / dma callbacks only need to be done once
|
||||||
|
*/
|
||||||
void __init arc_cache_init_master(void)
|
void __init arc_cache_init_master(void)
|
||||||
{
|
{
|
||||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||||
|
|
@ -1190,12 +1209,27 @@ void __ref arc_cache_init(void)
|
||||||
|
|
||||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||||
|
|
||||||
/*
|
|
||||||
* Only master CPU needs to execute rest of function:
|
|
||||||
* - Assume SMP so all cores will have same cache config so
|
|
||||||
* any geomtry checks will be same for all
|
|
||||||
* - IOC setup / dma callbacks only need to be setup once
|
|
||||||
*/
|
|
||||||
if (!cpu)
|
if (!cpu)
|
||||||
arc_cache_init_master();
|
arc_cache_init_master();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* In PAE regime, TLB and cache maintenance ops take wider addresses
|
||||||
|
* And even if PAE is not enabled in kernel, the upper 32-bits still need
|
||||||
|
* to be zeroed to keep the ops sane.
|
||||||
|
* As an optimization for more common !PAE enabled case, zero them out
|
||||||
|
* once at init, rather than checking/setting to 0 for every runtime op
|
||||||
|
*/
|
||||||
|
if (is_isa_arcv2() && pae40_exist_but_not_enab()) {
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE))
|
||||||
|
write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE))
|
||||||
|
write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
|
||||||
|
|
||||||
|
if (l2_line_sz) {
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
|
||||||
|
write_aux_reg(ARC_REG_SLC_RGN_START1, 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -117,7 +117,7 @@ static int arc_dma_mmap(struct device *dev, struct vm_area_struct *vma,
|
||||||
|
|
||||||
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
||||||
|
|
||||||
if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
|
if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
if (off < count && user_count <= (count - off)) {
|
if (off < count && user_count <= (count - off)) {
|
||||||
|
|
@ -153,6 +153,19 @@ static void _dma_cache_sync(phys_addr_t paddr, size_t size,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* arc_dma_map_page - map a portion of a page for streaming DMA
|
||||||
|
*
|
||||||
|
* Ensure that any data held in the cache is appropriately discarded
|
||||||
|
* or written back.
|
||||||
|
*
|
||||||
|
* The device owns this memory once this call has completed. The CPU
|
||||||
|
* can regain ownership by calling dma_unmap_page().
|
||||||
|
*
|
||||||
|
* Note: while it takes struct page as arg, caller can "abuse" it to pass
|
||||||
|
* a region larger than PAGE_SIZE, provided it is physically contiguous
|
||||||
|
* and this still works correctly
|
||||||
|
*/
|
||||||
static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
|
static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
|
||||||
unsigned long offset, size_t size, enum dma_data_direction dir,
|
unsigned long offset, size_t size, enum dma_data_direction dir,
|
||||||
unsigned long attrs)
|
unsigned long attrs)
|
||||||
|
|
@ -165,6 +178,24 @@ static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
|
||||||
return plat_phys_to_dma(dev, paddr);
|
return plat_phys_to_dma(dev, paddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* arc_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
|
||||||
|
*
|
||||||
|
* After this call, reads by the CPU to the buffer are guaranteed to see
|
||||||
|
* whatever the device wrote there.
|
||||||
|
*
|
||||||
|
* Note: historically this routine was not implemented for ARC
|
||||||
|
*/
|
||||||
|
static void arc_dma_unmap_page(struct device *dev, dma_addr_t handle,
|
||||||
|
size_t size, enum dma_data_direction dir,
|
||||||
|
unsigned long attrs)
|
||||||
|
{
|
||||||
|
phys_addr_t paddr = plat_dma_to_phys(dev, handle);
|
||||||
|
|
||||||
|
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
|
||||||
|
_dma_cache_sync(paddr, size, dir);
|
||||||
|
}
|
||||||
|
|
||||||
static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
|
static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
|
||||||
int nents, enum dma_data_direction dir, unsigned long attrs)
|
int nents, enum dma_data_direction dir, unsigned long attrs)
|
||||||
{
|
{
|
||||||
|
|
@ -178,6 +209,18 @@ static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
|
||||||
return nents;
|
return nents;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void arc_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
|
||||||
|
int nents, enum dma_data_direction dir,
|
||||||
|
unsigned long attrs)
|
||||||
|
{
|
||||||
|
struct scatterlist *s;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for_each_sg(sg, s, nents, i)
|
||||||
|
arc_dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir,
|
||||||
|
attrs);
|
||||||
|
}
|
||||||
|
|
||||||
static void arc_dma_sync_single_for_cpu(struct device *dev,
|
static void arc_dma_sync_single_for_cpu(struct device *dev,
|
||||||
dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
|
dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
|
||||||
{
|
{
|
||||||
|
|
@ -223,7 +266,9 @@ const struct dma_map_ops arc_dma_ops = {
|
||||||
.free = arc_dma_free,
|
.free = arc_dma_free,
|
||||||
.mmap = arc_dma_mmap,
|
.mmap = arc_dma_mmap,
|
||||||
.map_page = arc_dma_map_page,
|
.map_page = arc_dma_map_page,
|
||||||
|
.unmap_page = arc_dma_unmap_page,
|
||||||
.map_sg = arc_dma_map_sg,
|
.map_sg = arc_dma_map_sg,
|
||||||
|
.unmap_sg = arc_dma_unmap_sg,
|
||||||
.sync_single_for_device = arc_dma_sync_single_for_device,
|
.sync_single_for_device = arc_dma_sync_single_for_device,
|
||||||
.sync_single_for_cpu = arc_dma_sync_single_for_cpu,
|
.sync_single_for_cpu = arc_dma_sync_single_for_cpu,
|
||||||
.sync_sg_for_cpu = arc_dma_sync_sg_for_cpu,
|
.sync_sg_for_cpu = arc_dma_sync_sg_for_cpu,
|
||||||
|
|
|
||||||
|
|
@ -104,6 +104,8 @@
|
||||||
/* A copy of the ASID from the PID reg is kept in asid_cache */
|
/* A copy of the ASID from the PID reg is kept in asid_cache */
|
||||||
DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
|
DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
|
||||||
|
|
||||||
|
static int __read_mostly pae_exists;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Utility Routine to erase a J-TLB entry
|
* Utility Routine to erase a J-TLB entry
|
||||||
* Caller needs to setup Index Reg (manually or via getIndex)
|
* Caller needs to setup Index Reg (manually or via getIndex)
|
||||||
|
|
@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void)
|
||||||
mmu->u_dtlb = mmu4->u_dtlb * 4;
|
mmu->u_dtlb = mmu4->u_dtlb * 4;
|
||||||
mmu->u_itlb = mmu4->u_itlb * 4;
|
mmu->u_itlb = mmu4->u_itlb * 4;
|
||||||
mmu->sasid = mmu4->sasid;
|
mmu->sasid = mmu4->sasid;
|
||||||
mmu->pae = mmu4->pae;
|
pae_exists = mmu->pae = mmu4->pae;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
|
||||||
return buf;
|
return buf;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int pae40_exist_but_not_enab(void)
|
||||||
|
{
|
||||||
|
return pae_exists && !is_pae40_enabled();
|
||||||
|
}
|
||||||
|
|
||||||
void arc_mmu_init(void)
|
void arc_mmu_init(void)
|
||||||
{
|
{
|
||||||
char str[256];
|
char str[256];
|
||||||
|
|
@ -859,6 +866,9 @@ void arc_mmu_init(void)
|
||||||
/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
|
/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
|
||||||
write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
|
write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
if (pae40_exist_but_not_enab())
|
||||||
|
write_aux_reg(ARC_REG_TLBPD1HI, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -1,13 +0,0 @@
|
||||||
#
|
|
||||||
# Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or modify
|
|
||||||
# it under the terms of the GNU General Public License version 2 as
|
|
||||||
# published by the Free Software Foundation.
|
|
||||||
#
|
|
||||||
|
|
||||||
menuconfig ARC_PLAT_SIM
|
|
||||||
bool "ARC nSIM based simulation virtual platforms"
|
|
||||||
help
|
|
||||||
Support for nSIM based ARC simulation platforms
|
|
||||||
This includes the standalone nSIM (uart only) vs. System C OSCI VP
|
|
||||||
|
|
@ -20,11 +20,14 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static const char *simulation_compat[] __initconst = {
|
static const char *simulation_compat[] __initconst = {
|
||||||
|
#ifdef CONFIG_ISA_ARCOMPACT
|
||||||
"snps,nsim",
|
"snps,nsim",
|
||||||
"snps,nsim_hs",
|
|
||||||
"snps,nsimosci",
|
"snps,nsimosci",
|
||||||
|
#else
|
||||||
|
"snps,nsim_hs",
|
||||||
"snps,nsimosci_hs",
|
"snps,nsimosci_hs",
|
||||||
"snps,zebu_hs",
|
"snps,zebu_hs",
|
||||||
|
#endif
|
||||||
NULL,
|
NULL,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -380,7 +380,7 @@ config ARCH_EP93XX
|
||||||
bool "EP93xx-based"
|
bool "EP93xx-based"
|
||||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||||
select ARM_AMBA
|
select ARM_AMBA
|
||||||
select ARM_PATCH_PHYS_VIRT
|
imply ARM_PATCH_PHYS_VIRT
|
||||||
select ARM_VIC
|
select ARM_VIC
|
||||||
select AUTO_ZRELADDR
|
select AUTO_ZRELADDR
|
||||||
select CLKDEV_LOOKUP
|
select CLKDEV_LOOKUP
|
||||||
|
|
|
||||||
|
|
@ -75,7 +75,7 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pca0_pins>;
|
pinctrl-0 = <&pca0_pins>;
|
||||||
interrupt-parent = <&gpio0>;
|
interrupt-parent = <&gpio0>;
|
||||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
|
|
@ -87,7 +87,7 @@
|
||||||
compatible = "nxp,pca9555";
|
compatible = "nxp,pca9555";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
interrupt-parent = <&gpio0>;
|
interrupt-parent = <&gpio0>;
|
||||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
|
|
|
||||||
|
|
@ -301,25 +301,4 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
|
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
/* VPIF capture port */
|
|
||||||
port@0 {
|
|
||||||
vpif_input_ch0: endpoint@0 {
|
|
||||||
reg = <0>;
|
|
||||||
bus-width = <8>;
|
|
||||||
};
|
|
||||||
|
|
||||||
vpif_input_ch1: endpoint@1 {
|
|
||||||
reg = <1>;
|
|
||||||
bus-width = <8>;
|
|
||||||
data-shift = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
/* VPIF display port */
|
|
||||||
port@1 {
|
|
||||||
vpif_output_ch0: endpoint {
|
|
||||||
bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -318,11 +318,4 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&vpif_capture_pins>;
|
pinctrl-0 = <&vpif_capture_pins>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
/* VPIF capture port */
|
|
||||||
port {
|
|
||||||
vpif_ch0: endpoint {
|
|
||||||
bus-width = <8>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -68,6 +68,34 @@
|
||||||
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
|
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
nandflash_pins: nandflash_pins {
|
||||||
|
pinctrl-single,pins = <
|
||||||
|
DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
|
||||||
|
DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
|
||||||
|
DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
|
||||||
|
DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
|
||||||
|
DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
|
||||||
|
DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
|
||||||
|
DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
|
||||||
|
DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
|
||||||
|
DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
|
||||||
|
DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
|
||||||
|
DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
|
||||||
|
DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
|
||||||
|
DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
|
||||||
|
DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
|
||||||
|
DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
|
||||||
|
DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
|
||||||
|
DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
|
||||||
|
DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
|
||||||
|
DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
|
||||||
|
DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
|
||||||
|
DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
|
||||||
|
DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
|
||||||
|
DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
|
||||||
|
>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&i2c1 {
|
&i2c1 {
|
||||||
|
|
@ -90,6 +118,8 @@
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&nandflash_pins>;
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
compatible = "ti,omap2-nand";
|
compatible = "ti,omap2-nand";
|
||||||
|
|
@ -98,9 +128,11 @@
|
||||||
interrupt-parent = <&gpmc>;
|
interrupt-parent = <&gpmc>;
|
||||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
gpmc,sync-clk-ps = <0>;
|
gpmc,sync-clk-ps = <0>;
|
||||||
|
|
@ -164,7 +196,7 @@
|
||||||
vmmc-supply = <&vmmcsd_fixed>;
|
vmmc-supply = <&vmmcsd_fixed>;
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||||
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* At least dm8168-evm rev c won't support multipoint, later may */
|
/* At least dm8168-evm rev c won't support multipoint, later may */
|
||||||
|
|
|
||||||
|
|
@ -145,7 +145,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
elm: elm@48080000 {
|
elm: elm@48080000 {
|
||||||
compatible = "ti,816-elm";
|
compatible = "ti,am3352-elm";
|
||||||
ti,hwmods = "elm";
|
ti,hwmods = "elm";
|
||||||
reg = <0x48080000 0x2000>;
|
reg = <0x48080000 0x2000>;
|
||||||
interrupts = <4>;
|
interrupts = <4>;
|
||||||
|
|
|
||||||
|
|
@ -190,7 +190,7 @@
|
||||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
||||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||||
ti,impedance-control = <0x1f>;
|
ti,min-output-impedance;
|
||||||
};
|
};
|
||||||
|
|
||||||
dp83867_1: ethernet-phy@3 {
|
dp83867_1: ethernet-phy@3 {
|
||||||
|
|
@ -198,7 +198,7 @@
|
||||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
|
||||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
|
||||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
|
||||||
ti,impedance-control = <0x1f>;
|
ti,min-output-impedance;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -59,6 +59,9 @@
|
||||||
compatible = "samsung,exynos4210-audss-clock";
|
compatible = "samsung,exynos4210-audss-clock";
|
||||||
reg = <0x03810000 0x0C>;
|
reg = <0x03810000 0x0C>;
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
|
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
||||||
|
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
|
||||||
|
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
|
||||||
};
|
};
|
||||||
|
|
||||||
i2s0: i2s@03830000 {
|
i2s0: i2s@03830000 {
|
||||||
|
|
|
||||||
|
|
@ -266,6 +266,7 @@
|
||||||
|
|
||||||
&hdmicec {
|
&hdmicec {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
needs-hpd;
|
||||||
};
|
};
|
||||||
|
|
||||||
&hsi2c_4 {
|
&hsi2c_4 {
|
||||||
|
|
|
||||||
|
|
@ -297,6 +297,7 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
ranges;
|
||||||
|
|
||||||
adc: adc@50030800 {
|
adc: adc@50030800 {
|
||||||
compatible = "fsl,imx25-gcq";
|
compatible = "fsl,imx25-gcq";
|
||||||
|
|
|
||||||
|
|
@ -507,7 +507,7 @@
|
||||||
pinctrl_pcie: pciegrp {
|
pinctrl_pcie: pciegrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
/* PCIe reset */
|
/* PCIe reset */
|
||||||
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
|
MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0
|
||||||
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
|
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
@ -668,7 +668,7 @@
|
||||||
&pcie {
|
&pcie {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_pcie>;
|
pinctrl-0 = <&pinctrl_pcie>;
|
||||||
reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
|
reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -557,6 +557,14 @@
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pinctrl_spi4: spi4grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
|
||||||
|
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
|
||||||
|
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
||||||
pinctrl_tsc2046_pendown: tsc2046_pendown {
|
pinctrl_tsc2046_pendown: tsc2046_pendown {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
|
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
|
||||||
|
|
@ -697,13 +705,5 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
|
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
|
||||||
>;
|
>;
|
||||||
|
|
||||||
pinctrl_spi4: spi4grp {
|
|
||||||
fsl,pins = <
|
|
||||||
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
|
|
||||||
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
|
|
||||||
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -1126,8 +1126,8 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
gpu: mali@ffa30000 {
|
gpu: gpu@ffa30000 {
|
||||||
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
|
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||||
reg = <0xffa30000 0x10000>;
|
reg = <0xffa30000 0x10000>;
|
||||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
|
|
||||||
|
|
@ -303,7 +303,7 @@
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
atmel,smc = <&hsmc>;
|
atmel,smc = <&hsmc>;
|
||||||
reg = <0x10000000 0x10000000
|
reg = <0x10000000 0x10000000
|
||||||
0x40000000 0x30000000>;
|
0x60000000 0x30000000>;
|
||||||
ranges = <0x0 0x0 0x10000000 0x10000000
|
ranges = <0x0 0x0 0x10000000 0x10000000
|
||||||
0x1 0x0 0x60000000 0x10000000
|
0x1 0x0 0x60000000 0x10000000
|
||||||
0x2 0x0 0x70000000 0x10000000
|
0x2 0x0 0x70000000 0x10000000
|
||||||
|
|
@ -1048,18 +1048,18 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
hsmc: hsmc@f8014000 {
|
hsmc: hsmc@f8014000 {
|
||||||
compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
|
compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
|
||||||
reg = <0xf8014000 0x1000>;
|
reg = <0xf8014000 0x1000>;
|
||||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
|
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||||
clocks = <&hsmc_clk>;
|
clocks = <&hsmc_clk>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ranges;
|
ranges;
|
||||||
|
|
||||||
pmecc: ecc-engine@ffffc070 {
|
pmecc: ecc-engine@f8014070 {
|
||||||
compatible = "atmel,sama5d2-pmecc";
|
compatible = "atmel,sama5d2-pmecc";
|
||||||
reg = <0xffffc070 0x490>,
|
reg = <0xf8014070 0x490>,
|
||||||
<0xffffc500 0x100>;
|
<0xf8014500 0x100>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -44,7 +44,9 @@
|
||||||
|
|
||||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
|
||||||
#include <dt-bindings/clock/sun8i-r-ccu.h>
|
#include <dt-bindings/clock/sun8i-r-ccu.h>
|
||||||
|
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
|
|
@ -175,8 +177,8 @@
|
||||||
compatible = "allwinner,sun8i-a83t-dma";
|
compatible = "allwinner,sun8i-a83t-dma";
|
||||||
reg = <0x01c02000 0x1000>;
|
reg = <0x01c02000 0x1000>;
|
||||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&ccu 21>;
|
clocks = <&ccu CLK_BUS_DMA>;
|
||||||
resets = <&ccu 7>;
|
resets = <&ccu RST_BUS_DMA>;
|
||||||
#dma-cells = <1>;
|
#dma-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -195,7 +197,7 @@
|
||||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg = <0x01c20800 0x400>;
|
reg = <0x01c20800 0x400>;
|
||||||
clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
|
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
|
||||||
clock-names = "apb", "hosc", "losc";
|
clock-names = "apb", "hosc", "losc";
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
|
|
@ -247,8 +249,8 @@
|
||||||
"allwinner,sun8i-h3-spdif";
|
"allwinner,sun8i-h3-spdif";
|
||||||
reg = <0x01c21000 0x400>;
|
reg = <0x01c21000 0x400>;
|
||||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&ccu 44>, <&ccu 76>;
|
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
|
||||||
resets = <&ccu 32>;
|
resets = <&ccu RST_BUS_SPDIF>;
|
||||||
clock-names = "apb", "spdif";
|
clock-names = "apb", "spdif";
|
||||||
dmas = <&dma 2>;
|
dmas = <&dma 2>;
|
||||||
dma-names = "tx";
|
dma-names = "tx";
|
||||||
|
|
@ -263,8 +265,8 @@
|
||||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg-shift = <2>;
|
reg-shift = <2>;
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
clocks = <&ccu 53>;
|
clocks = <&ccu CLK_BUS_UART0>;
|
||||||
resets = <&ccu 40>;
|
resets = <&ccu RST_BUS_UART0>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -56,8 +56,6 @@
|
||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &uart0;
|
serial0 = &uart0;
|
||||||
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
|
|
||||||
ethernet0 = &emac;
|
|
||||||
ethernet1 = &xr819;
|
ethernet1 = &xr819;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -104,13 +102,6 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
&emac {
|
|
||||||
phy-handle = <&int_mii_phy>;
|
|
||||||
phy-mode = "mii";
|
|
||||||
allwinner,leds-active-low;
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
&mmc0 {
|
&mmc0 {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&mmc0_pins_a>;
|
pinctrl-0 = <&mmc0_pins_a>;
|
||||||
|
|
|
||||||
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Add table
Reference in a new issue