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https://github.com/Fishwaldo/Star64_linux.git
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Char/Misc driver fixes for 6.5-rc6
Here are some small char/misc driver fixes for 6.5-rc6 that resolve some reported issues. Included in here are: - bunch of iio driver fixes for reported problems - interconnect driver fixes - counter driver build fix - cardreader driver fixes - binder driver fixes - other tiny driver fixes All of these have been in linux-next for a while with no reported problems. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCZNdWFQ8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+yl9TACeOsUiS31nWuv+JS6Kljj5qZ0p+V0An0kmBw/+ FOQVIk0niv+Hnnb4WwvF =ZtpJ -----END PGP SIGNATURE----- Merge tag 'char-misc-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char / misc driver fixes from Greg KH: "Here are some small char/misc driver fixes for 6.5-rc6 that resolve some reported issues. Included in here are: - bunch of iio driver fixes for reported problems - interconnect driver fixes - counter driver build fix - cardreader driver fixes - binder driver fixes - other tiny driver fixes All of these have been in linux-next for a while with no reported problems" * tag 'char-misc-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (21 commits) misc: tps6594-esm: Disable ESM for rev 1 PMIC misc: rtsx: judge ASPM Mode to set PETXCFG Reg binder: fix memory leak in binder_init() iio: cros_ec: Fix the allocation size for cros_ec_command tools/counter: Makefile: Replace rmdir by rm to avoid make,clean failure iio: imu: lsm6dsx: Fix mount matrix retrieval iio: adc: meson: fix core clock enable/disable moment iio: core: Prevent invalid memory access when there is no parent iio: frequency: admv1013: propagate errors from regulator_get_voltage() counter: Fix menuconfig "Counter support" submenu entries disappearance dt-bindings: iio: adi,ad74115: remove ref from -nanoamp iio: adc: ina2xx: avoid NULL pointer dereference on OF device match iio: light: bu27008: Fix intensity data type iio: light: bu27008: Fix scale format iio: light: bu27034: Fix scale format iio: adc: ad7192: Fix ac excitation feature interconnect: qcom: sa8775p: add enable_mask for bcm nodes interconnect: qcom: sm8550: add enable_mask for bcm nodes interconnect: qcom: sm8450: add enable_mask for bcm nodes interconnect: qcom: Add support for mask-based BCMs ...
This commit is contained in:
commit
3feecb1b84
27 changed files with 148 additions and 103 deletions
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@ -216,7 +216,6 @@ properties:
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description: Whether to enable burnout current for EXT1.
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adi,ext1-burnout-current-nanoamp:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Burnout current in nanoamps to be applied to EXT1.
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enum: [0, 50, 500, 1000, 10000]
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@ -233,7 +232,6 @@ properties:
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description: Whether to enable burnout current for EXT2.
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adi,ext2-burnout-current-nanoamp:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Burnout current in nanoamps to be applied to EXT2.
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enum: [0, 50, 500, 1000, 10000]
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default: 0
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@ -249,7 +247,6 @@ properties:
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description: Whether to enable burnout current for VIOUT.
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adi,viout-burnout-current-nanoamp:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Burnout current in nanoamps to be applied to VIOUT.
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enum: [0, 1000, 10000]
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default: 0
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@ -6617,6 +6617,7 @@ err_init_binder_device_failed:
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err_alloc_device_names_failed:
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debugfs_remove_recursive(binder_debugfs_dir_entry_root);
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binder_alloc_shrinker_exit();
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return ret;
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}
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@ -1087,6 +1087,12 @@ int binder_alloc_shrinker_init(void)
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return ret;
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}
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void binder_alloc_shrinker_exit(void)
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{
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unregister_shrinker(&binder_shrinker);
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list_lru_destroy(&binder_alloc_lru);
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}
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/**
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* check_buffer() - verify that buffer/offset is safe to access
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* @alloc: binder_alloc for this proc
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@ -129,6 +129,7 @@ extern struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc,
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int pid);
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extern void binder_alloc_init(struct binder_alloc *alloc);
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extern int binder_alloc_shrinker_init(void);
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extern void binder_alloc_shrinker_exit(void);
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extern void binder_alloc_vma_close(struct binder_alloc *alloc);
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extern struct binder_buffer *
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binder_alloc_prepare_to_free(struct binder_alloc *alloc,
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@ -3,13 +3,6 @@
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# Counter devices
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#
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menuconfig COUNTER
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tristate "Counter support"
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help
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This enables counter device support through the Generic Counter
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interface. You only need to enable this, if you also want to enable
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one or more of the counter device drivers below.
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config I8254
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tristate
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select COUNTER
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@ -25,6 +18,13 @@ config I8254
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If built as a module its name will be i8254.
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menuconfig COUNTER
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tristate "Counter support"
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help
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This enables counter device support through the Generic Counter
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interface. You only need to enable this, if you also want to enable
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one or more of the counter device drivers below.
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if COUNTER
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config 104_QUAD_8
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@ -62,7 +62,6 @@
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#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
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#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
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#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
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#define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
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#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
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#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
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#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
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@ -91,6 +90,7 @@
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/* Configuration Register Bit Designations (AD7192_REG_CONF) */
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#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
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#define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
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#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
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#define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
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#define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
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@ -472,7 +472,7 @@ static ssize_t ad7192_show_ac_excitation(struct device *dev,
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad7192_state *st = iio_priv(indio_dev);
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return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
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return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX));
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}
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static ssize_t ad7192_show_bridge_switch(struct device *dev,
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@ -513,13 +513,13 @@ static ssize_t ad7192_set(struct device *dev,
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ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
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break;
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case AD7192_REG_MODE:
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case AD7192_REG_CONF:
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if (val)
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st->mode |= AD7192_MODE_ACX;
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st->conf |= AD7192_CONF_ACX;
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else
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st->mode &= ~AD7192_MODE_ACX;
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st->conf &= ~AD7192_CONF_ACX;
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ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
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ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
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break;
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default:
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ret = -EINVAL;
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@ -579,12 +579,11 @@ static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
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static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
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ad7192_show_ac_excitation, ad7192_set,
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AD7192_REG_MODE);
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AD7192_REG_CONF);
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static struct attribute *ad7192_attributes[] = {
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&iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
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&iio_dev_attr_bridge_switch_en.dev_attr.attr,
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&iio_dev_attr_ac_excitation_en.dev_attr.attr,
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NULL
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};
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@ -595,6 +594,7 @@ static const struct attribute_group ad7192_attribute_group = {
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static struct attribute *ad7195_attributes[] = {
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&iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
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&iio_dev_attr_bridge_switch_en.dev_attr.attr,
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&iio_dev_attr_ac_excitation_en.dev_attr.attr,
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NULL
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};
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@ -124,6 +124,7 @@ static const struct regmap_config ina2xx_regmap_config = {
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enum ina2xx_ids { ina219, ina226 };
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struct ina2xx_config {
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const char *name;
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u16 config_default;
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int calibration_value;
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int shunt_voltage_lsb; /* nV */
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@ -155,6 +156,7 @@ struct ina2xx_chip_info {
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static const struct ina2xx_config ina2xx_config[] = {
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[ina219] = {
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.name = "ina219",
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.config_default = INA219_CONFIG_DEFAULT,
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.calibration_value = 4096,
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.shunt_voltage_lsb = 10000,
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@ -164,6 +166,7 @@ static const struct ina2xx_config ina2xx_config[] = {
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.chip_id = ina219,
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},
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[ina226] = {
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.name = "ina226",
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.config_default = INA226_CONFIG_DEFAULT,
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.calibration_value = 2048,
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.shunt_voltage_lsb = 2500,
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@ -996,7 +999,7 @@ static int ina2xx_probe(struct i2c_client *client)
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/* Patch the current config register with default. */
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val = chip->config->config_default;
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if (id->driver_data == ina226) {
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if (type == ina226) {
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ina226_set_average(chip, INA226_DEFAULT_AVG, &val);
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ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val);
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ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val);
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@ -1015,7 +1018,7 @@ static int ina2xx_probe(struct i2c_client *client)
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}
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indio_dev->modes = INDIO_DIRECT_MODE;
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if (id->driver_data == ina226) {
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if (type == ina226) {
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indio_dev->channels = ina226_channels;
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indio_dev->num_channels = ARRAY_SIZE(ina226_channels);
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indio_dev->info = &ina226_info;
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@ -1024,7 +1027,7 @@ static int ina2xx_probe(struct i2c_client *client)
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indio_dev->num_channels = ARRAY_SIZE(ina219_channels);
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indio_dev->info = &ina219_info;
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}
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indio_dev->name = id->name;
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indio_dev->name = id ? id->name : chip->config->name;
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ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
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&ina2xx_setup_ops);
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|
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@ -916,12 +916,6 @@ static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
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goto err_vref;
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}
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ret = clk_prepare_enable(priv->core_clk);
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if (ret) {
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dev_err(dev, "failed to enable core clk\n");
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goto err_core_clk;
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}
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regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
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MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
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@ -948,8 +942,6 @@ err_adc_clk:
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
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MESON_SAR_ADC_REG3_ADC_EN, 0);
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meson_sar_adc_set_bandgap(indio_dev, false);
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clk_disable_unprepare(priv->core_clk);
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err_core_clk:
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regulator_disable(priv->vref);
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err_vref:
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meson_sar_adc_unlock(indio_dev);
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@ -977,8 +969,6 @@ static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
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meson_sar_adc_set_bandgap(indio_dev, false);
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clk_disable_unprepare(priv->core_clk);
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regulator_disable(priv->vref);
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if (!ret)
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@ -1211,7 +1201,7 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
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if (IS_ERR(priv->clkin))
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return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
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priv->core_clk = devm_clk_get(dev, "core");
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priv->core_clk = devm_clk_get_enabled(dev, "core");
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if (IS_ERR(priv->core_clk))
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return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
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|
@ -1294,15 +1284,26 @@ static int meson_sar_adc_remove(struct platform_device *pdev)
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static int meson_sar_adc_suspend(struct device *dev)
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{
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struct iio_dev *indio_dev = dev_get_drvdata(dev);
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struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
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|
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meson_sar_adc_hw_disable(indio_dev);
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|
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clk_disable_unprepare(priv->core_clk);
|
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|
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return 0;
|
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}
|
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|
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static int meson_sar_adc_resume(struct device *dev)
|
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{
|
||||
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
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struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->core_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable core clk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return meson_sar_adc_hw_enable(indio_dev);
|
||||
}
|
||||
|
|
|
@ -253,7 +253,7 @@ int cros_ec_sensors_core_init(struct platform_device *pdev,
|
|||
platform_set_drvdata(pdev, indio_dev);
|
||||
|
||||
state->ec = ec->ec_dev;
|
||||
state->msg = devm_kzalloc(&pdev->dev,
|
||||
state->msg = devm_kzalloc(&pdev->dev, sizeof(*state->msg) +
|
||||
max((u16)sizeof(struct ec_params_motion_sense),
|
||||
state->ec->max_response), GFP_KERNEL);
|
||||
if (!state->msg)
|
||||
|
|
|
@ -344,9 +344,12 @@ static int admv1013_update_quad_filters(struct admv1013_state *st)
|
|||
|
||||
static int admv1013_update_mixer_vgate(struct admv1013_state *st)
|
||||
{
|
||||
unsigned int vcm, mixer_vgate;
|
||||
unsigned int mixer_vgate;
|
||||
int vcm;
|
||||
|
||||
vcm = regulator_get_voltage(st->reg);
|
||||
if (vcm < 0)
|
||||
return vcm;
|
||||
|
||||
if (vcm < 1800000)
|
||||
mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;
|
||||
|
|
|
@ -2687,7 +2687,7 @@ unknown_format:
|
|||
static int lsm6dsx_get_acpi_mount_matrix(struct device *dev,
|
||||
struct iio_mount_matrix *orientation)
|
||||
{
|
||||
return false;
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1888,7 +1888,7 @@ static const struct iio_buffer_setup_ops noop_ring_setup_ops;
|
|||
int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod)
|
||||
{
|
||||
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
|
||||
struct fwnode_handle *fwnode;
|
||||
struct fwnode_handle *fwnode = NULL;
|
||||
int ret;
|
||||
|
||||
if (!indio_dev->info)
|
||||
|
@ -1899,7 +1899,8 @@ int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod)
|
|||
/* If the calling driver did not initialize firmware node, do it here */
|
||||
if (dev_fwnode(&indio_dev->dev))
|
||||
fwnode = dev_fwnode(&indio_dev->dev);
|
||||
else
|
||||
/* The default dummy IIO device has no parent */
|
||||
else if (indio_dev->dev.parent)
|
||||
fwnode = dev_fwnode(indio_dev->dev.parent);
|
||||
device_set_node(&indio_dev->dev, fwnode);
|
||||
|
||||
|
|
|
@ -190,7 +190,7 @@ static const struct iio_itime_sel_mul bu27008_itimes[] = {
|
|||
.address = BU27008_REG_##data##_LO, \
|
||||
.scan_index = BU27008_##color, \
|
||||
.scan_type = { \
|
||||
.sign = 's', \
|
||||
.sign = 'u', \
|
||||
.realbits = 16, \
|
||||
.storagebits = 16, \
|
||||
.endianness = IIO_LE, \
|
||||
|
@ -633,7 +633,7 @@ static int bu27008_try_find_new_time_gain(struct bu27008_data *data, int val,
|
|||
for (i = 0; i < data->gts.num_itime; i++) {
|
||||
new_time_sel = data->gts.itime_table[i].sel;
|
||||
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
|
||||
new_time_sel, val, val2 * 1000, gain_sel);
|
||||
new_time_sel, val, val2, gain_sel);
|
||||
if (!ret)
|
||||
break;
|
||||
}
|
||||
|
@ -662,7 +662,7 @@ static int bu27008_set_scale(struct bu27008_data *data,
|
|||
goto unlock_out;
|
||||
|
||||
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
|
||||
val, val2 * 1000, &gain_sel);
|
||||
val, val2, &gain_sel);
|
||||
if (ret) {
|
||||
ret = bu27008_try_find_new_time_gain(data, val, val2, &gain_sel);
|
||||
if (ret)
|
||||
|
@ -677,6 +677,21 @@ unlock_out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int bu27008_write_raw_get_fmt(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
long mask)
|
||||
{
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_SCALE:
|
||||
return IIO_VAL_INT_PLUS_NANO;
|
||||
case IIO_CHAN_INFO_INT_TIME:
|
||||
return IIO_VAL_INT_PLUS_MICRO;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int bu27008_write_raw(struct iio_dev *idev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int val, int val2, long mask)
|
||||
|
@ -756,6 +771,7 @@ static int bu27008_update_scan_mode(struct iio_dev *idev,
|
|||
static const struct iio_info bu27008_info = {
|
||||
.read_raw = &bu27008_read_raw,
|
||||
.write_raw = &bu27008_write_raw,
|
||||
.write_raw_get_fmt = &bu27008_write_raw_get_fmt,
|
||||
.read_avail = &bu27008_read_avail,
|
||||
.update_scan_mode = bu27008_update_scan_mode,
|
||||
.validate_trigger = iio_validate_own_trigger,
|
||||
|
|
|
@ -575,7 +575,7 @@ static int bu27034_set_scale(struct bu27034_data *data, int chan,
|
|||
return -EINVAL;
|
||||
|
||||
if (chan == BU27034_CHAN_ALS) {
|
||||
if (val == 0 && val2 == 1000)
|
||||
if (val == 0 && val2 == 1000000)
|
||||
return 0;
|
||||
|
||||
return -EINVAL;
|
||||
|
@ -587,7 +587,7 @@ static int bu27034_set_scale(struct bu27034_data *data, int chan,
|
|||
goto unlock_out;
|
||||
|
||||
ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts, time_sel,
|
||||
val, val2 * 1000, &gain_sel);
|
||||
val, val2, &gain_sel);
|
||||
if (ret) {
|
||||
/*
|
||||
* Could not support scale with given time. Need to change time.
|
||||
|
@ -624,7 +624,7 @@ static int bu27034_set_scale(struct bu27034_data *data, int chan,
|
|||
|
||||
/* Can we provide requested scale with this time? */
|
||||
ret = iio_gts_find_gain_sel_for_scale_using_time(
|
||||
&data->gts, new_time_sel, val, val2 * 1000,
|
||||
&data->gts, new_time_sel, val, val2,
|
||||
&gain_sel);
|
||||
if (ret)
|
||||
continue;
|
||||
|
@ -1217,6 +1217,21 @@ static int bu27034_read_raw(struct iio_dev *idev,
|
|||
}
|
||||
}
|
||||
|
||||
static int bu27034_write_raw_get_fmt(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
long mask)
|
||||
{
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_SCALE:
|
||||
return IIO_VAL_INT_PLUS_NANO;
|
||||
case IIO_CHAN_INFO_INT_TIME:
|
||||
return IIO_VAL_INT_PLUS_MICRO;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int bu27034_write_raw(struct iio_dev *idev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int val, int val2, long mask)
|
||||
|
@ -1267,6 +1282,7 @@ static int bu27034_read_avail(struct iio_dev *idev,
|
|||
static const struct iio_info bu27034_info = {
|
||||
.read_raw = &bu27034_read_raw,
|
||||
.write_raw = &bu27034_write_raw,
|
||||
.write_raw_get_fmt = &bu27034_write_raw_get_fmt,
|
||||
.read_avail = &bu27034_read_avail,
|
||||
};
|
||||
|
||||
|
|
|
@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
|
|||
|
||||
temp = agg_peak[bucket] * bcm->vote_scale;
|
||||
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
|
||||
|
||||
if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
|
||||
bcm->vote_x[bucket] = 0;
|
||||
bcm->vote_y[bucket] = bcm->enable_mask;
|
||||
}
|
||||
}
|
||||
|
||||
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
|
||||
|
|
|
@ -81,6 +81,7 @@ struct qcom_icc_node {
|
|||
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
|
||||
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
|
||||
* @vote_scale: scaling factor for vote_x and vote_y
|
||||
* @enable_mask: optional mask to send as vote instead of vote_x/vote_y
|
||||
* @dirty: flag used to indicate whether the bcm needs to be committed
|
||||
* @keepalive: flag used to indicate whether a keepalive is required
|
||||
* @aux_data: auxiliary data used when calculating threshold values and
|
||||
|
@ -97,6 +98,7 @@ struct qcom_icc_bcm {
|
|||
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
|
||||
u64 vote_scale;
|
||||
u32 enable_mask;
|
||||
bool dirty;
|
||||
bool keepalive;
|
||||
struct bcm_db aux_data;
|
||||
|
|
|
@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x8,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi },
|
||||
};
|
||||
|
|
|
@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x8,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi },
|
||||
};
|
||||
|
@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_cn0 = {
|
||||
.name = "CN0",
|
||||
.enable_mask = 0x1,
|
||||
.keepalive = true,
|
||||
.num_nodes = 55,
|
||||
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
|
||||
|
@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_co0 = {
|
||||
.name = "CO0",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
|
||||
};
|
||||
|
@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 12,
|
||||
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
|
||||
&qnm_camnoc_sf, &qnm_mdp,
|
||||
|
@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 7,
|
||||
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
|
||||
&qnm_nsp_gemnoc, &qnm_pcie,
|
||||
|
@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sn1 = {
|
||||
.name = "SN1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qhm_gic, &qxm_pimem,
|
||||
&xm_gic, &qns_gemnoc_gc },
|
||||
|
@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv_disp = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1_disp = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
|
||||
&qns_mem_noc_sf_disp },
|
||||
|
@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1_disp = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &qnm_pcie_disp },
|
||||
};
|
||||
|
|
|
@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x8,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi },
|
||||
};
|
||||
|
@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_cn0 = {
|
||||
.name = "CN0",
|
||||
.enable_mask = 0x1,
|
||||
.keepalive = true,
|
||||
.num_nodes = 54,
|
||||
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
|
||||
|
@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_co0 = {
|
||||
.name = "CO0",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
|
||||
};
|
||||
|
@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 8,
|
||||
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
|
||||
&qnm_camnoc_sf, &qnm_vapss_hcp,
|
||||
|
@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 13,
|
||||
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
|
||||
&chm_apps, &qnm_gpu,
|
||||
|
@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sn1 = {
|
||||
.name = "SN1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qhm_gic, &xm_gic,
|
||||
&qns_gemnoc_gc },
|
||||
|
@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv_disp = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_disp },
|
||||
};
|
||||
|
@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1_disp = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 2,
|
||||
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
|
||||
};
|
||||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_0 },
|
||||
};
|
||||
|
@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
|
||||
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
|
||||
|
@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
|
||||
&qnm_pcie_cam_ife_0 },
|
||||
|
@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_1 },
|
||||
};
|
||||
|
@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
|
||||
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
|
||||
|
@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
|
||||
&qnm_pcie_cam_ife_1 },
|
||||
|
@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
|
||||
.name = "ACV",
|
||||
.enable_mask = 0x0,
|
||||
.num_nodes = 1,
|
||||
.nodes = { &ebi_cam_ife_2 },
|
||||
};
|
||||
|
@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
|
||||
.name = "MM1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 4,
|
||||
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
|
||||
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
|
||||
|
@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
|
|||
|
||||
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
|
||||
.name = "SH1",
|
||||
.enable_mask = 0x1,
|
||||
.num_nodes = 3,
|
||||
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
|
||||
&qnm_pcie_cam_ife_2 },
|
||||
|
|
|
@ -195,7 +195,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
}
|
||||
}
|
||||
|
||||
if (option->force_clkreq_0)
|
||||
if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG)
|
||||
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
|
||||
else
|
||||
|
|
|
@ -435,17 +435,10 @@ static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
|
|||
option->ltr_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
|
||||
| PM_L1_1_EN | PM_L1_2_EN))
|
||||
option->force_clkreq_0 = false;
|
||||
else
|
||||
option->force_clkreq_0 = true;
|
||||
}
|
||||
|
||||
static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
|
||||
rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
|
||||
CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
|
||||
|
@ -476,17 +469,6 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
else
|
||||
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
|
||||
|
||||
/*
|
||||
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
|
||||
* to drive low, and we forcibly request clock.
|
||||
*/
|
||||
if (option->force_clkreq_0)
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
|
||||
else
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
|
||||
|
||||
rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
|
||||
|
||||
if (pcr->rtd3_en) {
|
||||
|
|
|
@ -327,12 +327,11 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
|
||||
* to drive low, and we forcibly request clock.
|
||||
*/
|
||||
if (option->force_clkreq_0)
|
||||
if (option->force_clkreq_0 && pcr->aspm_mode == ASPM_MODE_CFG)
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
|
||||
else
|
||||
|
|
|
@ -517,17 +517,10 @@ static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
|
|||
option->ltr_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
|
||||
| PM_L1_1_EN | PM_L1_2_EN))
|
||||
option->force_clkreq_0 = false;
|
||||
else
|
||||
option->force_clkreq_0 = true;
|
||||
}
|
||||
|
||||
static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
|
||||
/* Set mcu_cnt to 7 to ensure data can be sampled properly */
|
||||
rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
|
||||
|
@ -546,17 +539,6 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
|
||||
rts5260_init_hw(pcr);
|
||||
|
||||
/*
|
||||
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
|
||||
* to drive low, and we forcibly request clock.
|
||||
*/
|
||||
if (option->force_clkreq_0)
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
|
||||
else
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
|
||||
|
||||
rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -498,17 +498,10 @@ static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
|
|||
option->ltr_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
|
||||
| PM_L1_1_EN | PM_L1_2_EN))
|
||||
option->force_clkreq_0 = false;
|
||||
else
|
||||
option->force_clkreq_0 = true;
|
||||
}
|
||||
|
||||
static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
|
||||
{
|
||||
struct rtsx_cr_option *option = &pcr->option;
|
||||
u32 val;
|
||||
|
||||
rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
|
||||
|
@ -554,17 +547,6 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
|
|||
else
|
||||
rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
|
||||
|
||||
/*
|
||||
* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
|
||||
* to drive low, and we forcibly request clock.
|
||||
*/
|
||||
if (option->force_clkreq_0)
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
|
||||
else
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
|
||||
|
||||
rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
|
||||
|
||||
if (pcr->rtd3_en) {
|
||||
|
|
|
@ -1326,8 +1326,11 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
|
|||
return err;
|
||||
}
|
||||
|
||||
if (pcr->aspm_mode == ASPM_MODE_REG)
|
||||
if (pcr->aspm_mode == ASPM_MODE_REG) {
|
||||
rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
|
||||
rtsx_pci_write_register(pcr, PETXCFG,
|
||||
FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
|
||||
}
|
||||
|
||||
/* No CD interrupt if probing driver with card inserted.
|
||||
* So we need to initialize pcr->card_exist here.
|
||||
|
|
|
@ -13,6 +13,8 @@
|
|||
|
||||
#include <linux/mfd/tps6594.h>
|
||||
|
||||
#define TPS6594_DEV_REV_1 0x08
|
||||
|
||||
static irqreturn_t tps6594_esm_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct platform_device *pdev = dev_id;
|
||||
|
@ -32,11 +34,26 @@ static int tps6594_esm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
|
||||
struct device *dev = &pdev->dev;
|
||||
unsigned int rev;
|
||||
int irq;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < pdev->num_resources ; i++) {
|
||||
/*
|
||||
* Due to a bug in revision 1 of the PMIC, the GPIO3 used for the
|
||||
* SoC ESM function is used to power the load switch instead.
|
||||
* As a consequence, ESM can not be used on those PMIC.
|
||||
* Check the version and return an error in case of revision 1.
|
||||
*/
|
||||
ret = regmap_read(tps->regmap, TPS6594_REG_DEV_REV, &rev);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret,
|
||||
"Failed to read PMIC revision\n");
|
||||
if (rev == TPS6594_DEV_REV_1)
|
||||
return dev_err_probe(dev, -ENODEV,
|
||||
"ESM not supported for revision 1 PMIC\n");
|
||||
|
||||
for (i = 0; i < pdev->num_resources; i++) {
|
||||
irq = platform_get_irq_byname(pdev, pdev->resource[i].name);
|
||||
if (irq < 0)
|
||||
return dev_err_probe(dev, irq, "Failed to get %s irq\n",
|
||||
|
|
|
@ -40,7 +40,8 @@ $(OUTPUT)counter_example: $(COUNTER_EXAMPLE)
|
|||
clean:
|
||||
rm -f $(ALL_PROGRAMS)
|
||||
rm -rf $(OUTPUT)include/linux/counter.h
|
||||
rmdir -p $(OUTPUT)include/linux
|
||||
rm -df $(OUTPUT)include/linux
|
||||
rm -df $(OUTPUT)include
|
||||
find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete
|
||||
|
||||
install: $(ALL_PROGRAMS)
|
||||
|
|
Loading…
Add table
Reference in a new issue