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powerpc/bpf: Reallocate BPF registers to volatile registers when possible on PPC32
When the BPF routine doesn't call any function, the non volatile registers can be reallocated to volatile registers in order to avoid having to save them/restore on the stack. Before this patch, the test #359 ADD default X is: 0: 7c 64 1b 78 mr r4,r3 4: 38 60 00 00 li r3,0 8: 94 21 ff b0 stwu r1,-80(r1) c: 60 00 00 00 nop 10: 92 e1 00 2c stw r23,44(r1) 14: 93 01 00 30 stw r24,48(r1) 18: 93 21 00 34 stw r25,52(r1) 1c: 93 41 00 38 stw r26,56(r1) 20: 39 80 00 00 li r12,0 24: 39 60 00 00 li r11,0 28: 3b 40 00 00 li r26,0 2c: 3b 20 00 00 li r25,0 30: 7c 98 23 78 mr r24,r4 34: 7c 77 1b 78 mr r23,r3 38: 39 80 00 42 li r12,66 3c: 39 60 00 00 li r11,0 40: 7d 8c d2 14 add r12,r12,r26 44: 39 60 00 00 li r11,0 48: 7d 83 63 78 mr r3,r12 4c: 82 e1 00 2c lwz r23,44(r1) 50: 83 01 00 30 lwz r24,48(r1) 54: 83 21 00 34 lwz r25,52(r1) 58: 83 41 00 38 lwz r26,56(r1) 5c: 38 21 00 50 addi r1,r1,80 60: 4e 80 00 20 blr After this patch, the same test has become: 0: 7c 64 1b 78 mr r4,r3 4: 38 60 00 00 li r3,0 8: 94 21 ff b0 stwu r1,-80(r1) c: 60 00 00 00 nop 10: 39 80 00 00 li r12,0 14: 39 60 00 00 li r11,0 18: 39 00 00 00 li r8,0 1c: 38 e0 00 00 li r7,0 20: 7c 86 23 78 mr r6,r4 24: 7c 65 1b 78 mr r5,r3 28: 39 80 00 42 li r12,66 2c: 39 60 00 00 li r11,0 30: 7d 8c 42 14 add r12,r12,r8 34: 39 60 00 00 li r11,0 38: 7d 83 63 78 mr r3,r12 3c: 38 21 00 50 addi r1,r1,80 40: 4e 80 00 20 blr Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/b94562d7d2bb21aec89de0c40bb3cd91054b65a2.1616430991.git.christophe.leroy@csgroup.eu
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51c66ad849
commit
40272035e1
5 changed files with 51 additions and 3 deletions
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@ -116,6 +116,15 @@ static inline bool is_nearbranch(int offset)
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#define SEEN_STACK 0x40000000 /* uses BPF stack */
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#define SEEN_TAILCALL 0x80000000 /* uses tail calls */
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#define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */
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#define SEEN_NVREG_MASK 0x0003ffff /* Non volatile registers r14-r31 */
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#ifdef CONFIG_PPC64
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extern const int b2p[MAX_BPF_JIT_REG + 2];
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#else
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extern const int b2p[MAX_BPF_JIT_REG + 1];
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#endif
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struct codegen_context {
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/*
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* This is used to track register usage as well
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@ -129,6 +138,7 @@ struct codegen_context {
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unsigned int seen;
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unsigned int idx;
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unsigned int stack_size;
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int b2p[ARRAY_SIZE(b2p)];
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};
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static inline void bpf_flush_icache(void *start, void *end)
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@ -147,11 +157,17 @@ static inline void bpf_set_seen_register(struct codegen_context *ctx, int i)
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ctx->seen |= 1 << (31 - i);
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}
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static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i)
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{
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ctx->seen &= ~(1 << (31 - i));
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}
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void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func);
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int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx,
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u32 *addrs, bool extra_pass);
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx);
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void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx);
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void bpf_jit_realloc_regs(struct codegen_context *ctx);
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#endif
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@ -39,7 +39,7 @@
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
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/* BPF to ppc register mappings */
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static const int b2p[] = {
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const int b2p[MAX_BPF_JIT_REG + 2] = {
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/* function return value */
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[BPF_REG_0] = 8,
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/* function arguments */
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@ -143,6 +143,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
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}
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memset(&cgctx, 0, sizeof(struct codegen_context));
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memcpy(cgctx.b2p, b2p, sizeof(cgctx.b2p));
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/* Make sure that the stack is quadword aligned. */
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cgctx.stack_size = round_up(fp->aux->stack_depth, 16);
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@ -167,6 +168,7 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
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}
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}
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bpf_jit_realloc_regs(&cgctx);
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/*
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* Pretend to build prologue, given the features we've seen. This will
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* update ctgtx.idx as it pretends to output instructions, then we can
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@ -37,7 +37,7 @@
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#define TMP_REG (MAX_BPF_JIT_REG + 0)
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/* BPF to ppc register mappings */
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static const int b2p[] = {
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const int b2p[MAX_BPF_JIT_REG + 1] = {
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/* function return value */
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[BPF_REG_0] = 12,
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/* function arguments */
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@ -60,7 +60,7 @@ static const int b2p[] = {
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static int bpf_to_ppc(struct codegen_context *ctx, int reg)
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{
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return b2p[reg];
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return ctx->b2p[reg];
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}
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/* PPC NVR range -- update this if we ever use NVRs below r17 */
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@ -77,6 +77,32 @@ static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg)
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return BPF_PPC_STACKFRAME(ctx) - 4;
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}
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void bpf_jit_realloc_regs(struct codegen_context *ctx)
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{
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if (ctx->seen & SEEN_FUNC)
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return;
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while (ctx->seen & SEEN_NVREG_MASK &&
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(ctx->seen & SEEN_VREG_MASK) != SEEN_VREG_MASK) {
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int old = 32 - fls(ctx->seen & (SEEN_NVREG_MASK & 0xaaaaaaab));
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int new = 32 - fls(~ctx->seen & (SEEN_VREG_MASK & 0xaaaaaaaa));
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int i;
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for (i = BPF_REG_0; i <= TMP_REG; i++) {
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if (ctx->b2p[i] != old)
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continue;
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ctx->b2p[i] = new;
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bpf_set_seen_register(ctx, new);
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bpf_clear_seen_register(ctx, old);
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if (i != TMP_REG) {
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bpf_set_seen_register(ctx, new - 1);
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bpf_clear_seen_register(ctx, old - 1);
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}
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break;
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}
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}
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}
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx)
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{
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int i;
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@ -64,6 +64,10 @@ static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg)
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BUG();
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}
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void bpf_jit_realloc_regs(struct codegen_context *ctx)
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{
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}
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void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx)
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{
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int i;
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