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drivers/pwm: Add SiFive PWM PTC driver
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3 changed files with 301 additions and 0 deletions
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@ -491,6 +491,16 @@ config PWM_SIFIVE
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To compile this driver as a module, choose M here: the module
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will be called pwm-sifive.
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config PWM_SIFIVE_PTC
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tristate "SiFive PWM PTC support"
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depends on OF
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depends on COMMON_CLK
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help
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Generic PWM framework driver for SiFive SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-sifive-ptc.
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config PWM_SL28CPLD
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tristate "Kontron sl28cpld PWM support"
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depends on MFD_SL28CPLD || COMPILE_TEST
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@ -45,6 +45,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
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obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
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obj-$(CONFIG_PWM_SIFIVE_PTC) += pwm-sifive-ptc.o
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obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
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obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
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obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
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290
drivers/pwm/pwm-sifive-ptc.c
Normal file
290
drivers/pwm/pwm-sifive-ptc.c
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@ -0,0 +1,290 @@
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/*
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* Copyright (C) 2018 SiFive, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2, as published by
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* the Free Software Foundation.
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*/
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#include <dt-bindings/pwm/pwm.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#define PTC_DEBUG 0
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/* max channel of pwm */
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#define MAX_PWM 8
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/* PTC Register offsets */
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#define REG_RPTC_CNTR 0x0
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#define REG_RPTC_HRC 0x4
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#define REG_RPTC_LRC 0x8
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#define REG_RPTC_CTRL 0xC
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/* Bit for PWM clock */
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#define BIT_PWM_CLOCK_EN 31
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/* Bit for clock gen soft reset */
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#define BIT_CLK_GEN_SOFT_RESET 13
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#define NS_1 1000000000
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/* Access PTC register (cntr hrc lrc and ctrl) ,need to replace PWM_BASE_ADDR */
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#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + ((N>3)?((N-4)*0x10+(1<<15)):(N*0x10)))
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#define REG_PTC_RPTC_CNTR(base,N) (REG_PTC_BASE_ADDR_SUB(base,N))
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#define REG_PTC_RPTC_HRC(base,N) (REG_PTC_BASE_ADDR_SUB(base,N) + 0x4)
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#define REG_PTC_RPTC_LRC(base,N) (REG_PTC_BASE_ADDR_SUB(base,N) + 0x8)
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#define REG_PTC_RPTC_CTRL(base,N) (REG_PTC_BASE_ADDR_SUB(base,N) + 0xC)
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/* pwm ptc device */
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struct sifive_pwm_ptc_device {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *regs;
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int irq;
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/* apb clock frequency , from dts */
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unsigned int approx_period;
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};
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static inline struct sifive_pwm_ptc_device *chip_to_sifive_ptc(struct pwm_chip *c)
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{
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return container_of(c, struct sifive_pwm_ptc_device, chip);
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}
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static void sifive_pwm_ptc_get_state(struct pwm_chip *chip, struct pwm_device *dev, struct pwm_state *state)
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{
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struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
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uint32_t data_lrc;
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uint32_t data_hrc;
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uint32_t pwm_clk_ns = 0;
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/* get lrc and hrc data from registe*/
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data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
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data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
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/* how many ns does apb clock elapse */
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pwm_clk_ns = NS_1 / pwm->approx_period;
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/* pwm period(ns) */
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state->period = data_lrc*pwm_clk_ns;
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/* duty cycle(ns) ,means high level eclapse ns if it is normal polarity */
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state->duty_cycle = data_hrc*pwm_clk_ns;
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/* polarity,we don't use it now because it is not in dts */
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state->polarity = PWM_POLARITY_NORMAL;
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/* enabled or not */
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state->enabled = 1;
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#ifdef PTC_DEBUG
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printk("sifive_pwm_ptc_get_state in,no:%d....\r\n",dev->hwpwm);
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printk("data_hrc:0x%x 0x%x \n", data_hrc, data_lrc);
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printk("period:%llu\r\n",state->period);
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printk("duty_cycle:%llu\r\n",state->duty_cycle);
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printk("polarity:%d\r\n",state->polarity);
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printk("enabled:%d\r\n",state->enabled);
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#endif
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}
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static int sifive_pwm_ptc_apply(struct pwm_chip *chip, struct pwm_device *dev, struct pwm_state *state)
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{
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struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
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uint32_t pwm_clk_ns = 0;
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uint32_t data_hrc = 0;
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uint32_t data_lrc = 0;
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uint32_t period_data = 0;
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uint32_t duty_data = 0;
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void __iomem* reg_addr;
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#if PTC_DEBUG
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printk("sifive_pwm_ptc_apply in,no:%d....\r\n",dev->hwpwm);
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printk("set parameter......\r\n");
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printk("period:%d\r\n",state->period);
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printk("duty_cycle:%d\r\n",state->duty_cycle);
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printk("polarity:%d\r\n",state->polarity);
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printk("enabled:%d\r\n",state->enabled);
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#endif
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/* duty_cycle should be less or equal than period */
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if(state->duty_cycle > state->period)
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state->duty_cycle = state->period;
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/* calculate pwm real period (ns) */
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pwm_clk_ns = NS_1 / pwm->approx_period;
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#if PTC_DEBUG
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printk("approx_period,:%d,pwm_clk_ns:%d\r\n",pwm->approx_period,pwm_clk_ns);
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#endif
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/* calculate period count */
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period_data = state->period / pwm_clk_ns;
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if (!state->enabled)
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/* if is unenable,just set duty_dat to 0 , means low level always */
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duty_data = 0;
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else
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/* calculate duty count*/
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duty_data = state->duty_cycle / pwm_clk_ns;
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#if PTC_DEBUG
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printk("period_data:%d,duty_data:%d\r\n",period_data,duty_data);
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#endif
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if(state->polarity == PWM_POLARITY_NORMAL)
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/* calculate data_hrc */
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data_hrc = period_data - duty_data;
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else
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/* calculate data_hrc */
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data_hrc = duty_data;
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data_lrc = period_data;
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/* set hrc */
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reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_config]reg_addr:0x%lx,data:%d....\n",reg_addr,data_hrc);
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#endif
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iowrite32(data_hrc, reg_addr);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_config]hrc ok....\n");
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#endif
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/* set lrc */
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reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_config]reg_addr:0x%lx,data:%d....\n",reg_addr,data_lrc);
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#endif
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iowrite32(data_lrc, reg_addr);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_config]lrc ok....\n");
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#endif
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return 0;
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}
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static const struct pwm_ops sifive_pwm_ptc_ops = {
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.get_state = sifive_pwm_ptc_get_state,
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.apply = (void *)sifive_pwm_ptc_apply,
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.owner = THIS_MODULE,
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};
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static int sifive_pwm_ptc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct sifive_pwm_ptc_device *pwm;
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struct pwm_chip *chip;
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struct resource *res;
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int ret;
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#if PTC_DEBUG
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printk("sifive_pwm_ptc_probe in....\r\n");
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#endif
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pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm) {
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dev_err(dev, "Out of memory\n");
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return -ENOMEM;
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}
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chip = &pwm->chip;
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chip->dev = dev;
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chip->ops = &sifive_pwm_ptc_ops;
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/* how many parameters can be transfered to ptc,need to fix */
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chip->of_pwm_n_cells = 3;
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chip->base = -1;
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/* get pwm channels count, max value is 8 */
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ret = of_property_read_u32(node, "starfive,npwm", &chip->npwm);
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if (ret < 0 || chip->npwm > MAX_PWM)
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chip->npwm = MAX_PWM;
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_probe] npwm:0x%lx....\r\n",chip->npwm);
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#endif
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/* get apb clock frequency */
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ret = of_property_read_u32(node, "sifive,approx-period", &pwm->approx_period);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_probe] approx_period:%d....\r\n",pwm->approx_period);
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#endif
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/* get IO base address*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_probe] res start:0x%lx,end:0x%lx....\r\n",res->start,res->end);
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#endif
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pwm->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(pwm->regs))
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{
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dev_err(dev, "Unable to map IO resources\n");
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return PTR_ERR(pwm->regs);
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}
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#if PTC_DEBUG
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printk("[sifive_pwm_ptc_probe] regs:0x%lx....\r\n",pwm->regs);
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#endif
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pwm->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pwm->clk)) {
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dev_err(dev, "Unable to find controller clock\n");
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return PTR_ERR(pwm->clk);
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}
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/* after add,it will display as /sys/class/pwm/pwmchip0,0 is chip->base
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* after execute echo 0 > export in , pwm0 can be seen */
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ret = pwmchip_add(chip);
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if (ret < 0) {
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dev_err(dev, "cannot register PTC: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pwm);
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#if PTC_DEBUG
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printk("SiFive PWM PTC chip registered %d PWMs\n", chip->npwm);
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#endif
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return 0;
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}
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static int sifive_pwm_ptc_remove(struct platform_device *dev)
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{
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struct sifive_pwm_ptc_device *pwm = platform_get_drvdata(dev);
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struct pwm_chip *chip = &pwm->chip;
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return pwmchip_remove(chip);
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}
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static const struct of_device_id sifive_pwm_ptc_of_match[] = {
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{ .compatible = "sifive,pwm0" },
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{ .compatible = "starfive,pwm0" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sifive_pwm_ptc_of_match);
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static struct platform_driver sifive_pwm_ptc_driver = {
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.probe = sifive_pwm_ptc_probe,
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.remove = sifive_pwm_ptc_remove,
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.driver = {
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.name = "pwm-sifive-ptc",
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.of_match_table = of_match_ptr(sifive_pwm_ptc_of_match),
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},
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};
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module_platform_driver(sifive_pwm_ptc_driver);
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MODULE_DESCRIPTION("SiFive PWM PTC driver");
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MODULE_LICENSE("GPL v2");
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