RISC-V: Support CPUID for risc-v in perf

This patch creates the header.c file for the risc-v architecture and introduces support for
PMU identification through sysfs.
It is now possible to configure pmu-events in risc-v.

Depends on patch [1], that introduces the id sysfs file.

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
This commit is contained in:
João Mário Domingos 2021-11-16 15:48:10 +00:00 committed by Hal Feng
parent 6f46d9c4c1
commit 4390f00ffe

View file

@ -18,6 +18,23 @@
#include <asm/sbi.h>
PMU_FORMAT_ATTR(event, "config:0-63");
static struct attribute *riscv_arch_formats_attr[] = {
&format_attr_event.attr,
NULL,
};
static struct attribute_group riscv_pmu_format_group = {
.name = "format",
.attrs = riscv_arch_formats_attr,
};
static const struct attribute_group *riscv_pmu_attr_groups[] = {
&riscv_pmu_format_group,
NULL,
};
static bool riscv_perf_user_access(struct perf_event *event)
{
return ((event->attr.type == PERF_TYPE_HARDWARE) ||
@ -414,6 +431,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
cpuc->events[i] = NULL;
}
pmu->pmu = (struct pmu) {
.attr_groups = riscv_pmu_attr_groups,
.event_init = riscv_pmu_event_init,
.event_mapped = riscv_pmu_event_mapped,
.event_unmapped = riscv_pmu_event_unmapped,