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RISC-V: Support CPUID for risc-v in perf
This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt> Signed-off-by: minda.chen <minda.chen@starfivetech.com>
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1 changed files with 18 additions and 0 deletions
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@ -18,6 +18,23 @@
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#include <asm/sbi.h>
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PMU_FORMAT_ATTR(event, "config:0-63");
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static struct attribute *riscv_arch_formats_attr[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group riscv_pmu_format_group = {
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.name = "format",
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.attrs = riscv_arch_formats_attr,
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};
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static const struct attribute_group *riscv_pmu_attr_groups[] = {
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&riscv_pmu_format_group,
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NULL,
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};
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static bool riscv_perf_user_access(struct perf_event *event)
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{
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return ((event->attr.type == PERF_TYPE_HARDWARE) ||
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@ -414,6 +431,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
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cpuc->events[i] = NULL;
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}
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pmu->pmu = (struct pmu) {
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.attr_groups = riscv_pmu_attr_groups,
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.event_init = riscv_pmu_event_init,
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.event_mapped = riscv_pmu_event_mapped,
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.event_unmapped = riscv_pmu_event_unmapped,
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