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drm/amdgpu: fix the build on big endian

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Some leftover copy and pastes from radeon that never
got updated.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2015-06-09 09:58:23 -04:00
parent 675da0ddd6
commit 454fc95e84
2 changed files with 5 additions and 3 deletions
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3
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
View file

@ -411,7 +411,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
rb_bufsz = order_base_2(ring->ring_size / 4); rb_bufsz = order_base_2(ring->ring_size / 4);
rb_cntl = rb_bufsz << 1; rb_cntl = rb_bufsz << 1;
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
#endif #endif
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

5
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View file

@ -2881,7 +2881,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
rb_bufsz = order_base_2(ring->ring_size / 8); rb_bufsz = order_base_2(ring->ring_size / 8);
tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
tmp |= BUF_SWAP_32BIT; tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
#endif #endif
WREG32(mmCP_RB0_CNTL, tmp); WREG32(mmCP_RB0_CNTL, tmp);
@ -3400,7 +3400,8 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
mqd->queue_state.cp_hqd_pq_control |= mqd->queue_state.cp_hqd_pq_control |=
(order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; mqd->queue_state.cp_hqd_pq_control |=
2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
#endif #endif
mqd->queue_state.cp_hqd_pq_control &= mqd->queue_state.cp_hqd_pq_control &=
~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |