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x86/bugs: Add asm helpers for executing VERW
commit baf8361e54550a48a7087b603313ad013cc13386 upstream. MDS mitigation requires clearing the CPU buffers before returning to user. This needs to be done late in the exit-to-user path. Current location of VERW leaves a possibility of kernel data ending up in CPU buffers for memory accesses done after VERW such as: 1. Kernel data accessed by an NMI between VERW and return-to-user can remain in CPU buffers since NMI returning to kernel does not execute VERW to clear CPU buffers. 2. Alyssa reported that after VERW is executed, CONFIG_GCC_PLUGIN_STACKLEAK=y scrubs the stack used by a system call. Memory accesses during stack scrubbing can move kernel stack contents into CPU buffers. 3. When caller saved registers are restored after a return from function executing VERW, the kernel stack accesses can remain in CPU buffers(since they occur after VERW). To fix this VERW needs to be moved very late in exit-to-user path. In preparation for moving VERW to entry/exit asm code, create macros that can be used in asm. Also make VERW patching depend on a new feature flag X86_FEATURE_CLEAR_CPU_BUF. Reported-by: Alyssa Milburn <alyssa.milburn@intel.com> Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Suggested-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: https://lore.kernel.org/all/20240213-delay-verw-v8-1-a6216d83edb7%40linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3 changed files with 37 additions and 1 deletions
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@ -6,6 +6,9 @@
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#include <linux/linkage.h>
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#include <asm/export.h>
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#include <asm/msr-index.h>
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#include <asm/unwind_hints.h>
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#include <asm/segment.h>
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#include <asm/cache.h>
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.pushsection .noinstr.text, "ax"
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@ -20,3 +23,23 @@ SYM_FUNC_END(entry_ibpb)
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EXPORT_SYMBOL_GPL(entry_ibpb);
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.popsection
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/*
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* Define the VERW operand that is disguised as entry code so that
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* it can be referenced with KPTI enabled. This ensure VERW can be
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* used late in exit-to-user path after page tables are switched.
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*/
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.pushsection .entry.text, "ax"
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.align L1_CACHE_BYTES, 0xcc
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SYM_CODE_START_NOALIGN(mds_verw_sel)
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UNWIND_HINT_UNDEFINED
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ANNOTATE_NOENDBR
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.word __KERNEL_DS
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.align L1_CACHE_BYTES, 0xcc
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SYM_CODE_END(mds_verw_sel);
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/* For KVM */
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EXPORT_SYMBOL_GPL(mds_verw_sel);
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.popsection
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@ -97,7 +97,7 @@
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
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/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* "" Clear CPU buffers using VERW */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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@ -329,6 +329,17 @@
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#endif
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.endm
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/*
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* Macro to execute VERW instruction that mitigate transient data sampling
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* attacks such as MDS. On affected systems a microcode update overloaded VERW
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* instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF.
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*
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* Note: Only the memory operand variant of VERW clears the CPU buffers.
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*/
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.macro CLEAR_CPU_BUFFERS
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ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLEAR_CPU_BUF
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_RETPOLINE_SAFE \
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@ -545,6 +556,8 @@ DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
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DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
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extern u16 mds_verw_sel;
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#include <asm/segment.h>
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/**
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