mirror of
https://github.com/Fishwaldo/Star64_linux.git
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drm/i915/audio: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ca53d8a5ecd1045325447b728376c8aa2891905f.1579871655.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
70a221b242
commit
49e659bcae
1 changed files with 58 additions and 54 deletions
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@ -291,18 +291,18 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
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u32 tmp;
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int i;
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tmp = I915_READ(reg_eldv);
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tmp = intel_de_read(dev_priv, reg_eldv);
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tmp &= bits_eldv;
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if (!tmp)
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return false;
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tmp = I915_READ(reg_elda);
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tmp = intel_de_read(dev_priv, reg_elda);
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tmp &= ~bits_elda;
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I915_WRITE(reg_elda, tmp);
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intel_de_write(dev_priv, reg_elda, tmp);
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for (i = 0; i < drm_eld_size(eld) / 4; i++)
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if (I915_READ(reg_edid) != *((const u32 *)eld + i))
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if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i))
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return false;
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return true;
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@ -317,16 +317,16 @@ static void g4x_audio_codec_disable(struct intel_encoder *encoder,
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drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n");
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tmp = I915_READ(G4X_AUD_VID_DID);
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tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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eldv = G4X_ELDV_DEVCTG;
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/* Invalidate ELD */
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
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tmp &= ~eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
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}
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static void g4x_audio_codec_enable(struct intel_encoder *encoder,
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@ -343,7 +343,7 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder,
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drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n",
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drm_eld_size(eld));
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tmp = I915_READ(G4X_AUD_VID_DID);
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tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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@ -355,19 +355,20 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder,
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G4X_HDMIW_HDMIEDID))
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return;
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
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tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
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len = (tmp >> 9) & 0x1f; /* ELD buffer size */
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
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len = min(drm_eld_size(eld) / 4, len);
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drm_dbg(&dev_priv->drm, "ELD size %d\n", len);
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for (i = 0; i < len; i++)
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I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
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intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
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*((const u32 *)eld + i));
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
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tmp |= eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
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}
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static void
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@ -390,7 +391,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
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else
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drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n");
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tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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@ -402,9 +403,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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}
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I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
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tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
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tmp &= ~AUD_CONFIG_M_MASK;
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tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
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tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
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@ -415,7 +416,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
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tmp |= AUD_M_CTS_M_PROG_ENABLE;
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}
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I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
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}
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static void
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@ -431,7 +432,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
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rate = acomp ? acomp->aud_sample_rate[port] : 0;
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tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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@ -448,16 +449,16 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
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drm_dbg_kms(&dev_priv->drm, "using automatic N\n");
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}
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I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
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/*
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* Let's disable "Enable CTS or M Prog bit"
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* and let HW calculate the value
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*/
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tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
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tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
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tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
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I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
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}
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static void
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@ -484,20 +485,20 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
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mutex_lock(&dev_priv->av_mutex);
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/* Disable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_crtc_has_dp_encoder(old_crtc_state))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
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/* Invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
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tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
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tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
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mutex_unlock(&dev_priv->av_mutex);
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}
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@ -520,10 +521,10 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
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mutex_lock(&dev_priv->av_mutex);
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/* Enable audio presence detect, invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
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tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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@ -533,19 +534,20 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
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*/
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/* Reset ELD write address */
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tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
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tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder));
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
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intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min(drm_eld_size(eld), 84);
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for (i = 0; i < len / 4; i++)
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I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i));
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intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder),
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*((const u32 *)eld + i));
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/* ELD valid */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_ELD_VALID(cpu_transcoder);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/* Enable timestamps */
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hsw_audio_config_update(encoder, crtc_state);
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@ -584,21 +586,21 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
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}
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/* Disable timestamps */
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tmp = I915_READ(aud_config);
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tmp = intel_de_read(dev_priv, aud_config);
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_crtc_has_dp_encoder(old_crtc_state))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(aud_config, tmp);
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intel_de_write(dev_priv, aud_config, tmp);
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eldv = IBX_ELD_VALID(port);
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/* Invalidate ELD */
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tmp = I915_READ(aud_cntrl_st2);
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tmp = intel_de_read(dev_priv, aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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intel_de_write(dev_priv, aud_cntrl_st2, tmp);
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}
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static void ilk_audio_codec_enable(struct intel_encoder *encoder,
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@ -651,27 +653,28 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
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eldv = IBX_ELD_VALID(port);
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/* Invalidate ELD */
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tmp = I915_READ(aud_cntrl_st2);
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tmp = intel_de_read(dev_priv, aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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intel_de_write(dev_priv, aud_cntrl_st2, tmp);
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/* Reset ELD write address */
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tmp = I915_READ(aud_cntl_st);
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tmp = intel_de_read(dev_priv, aud_cntl_st);
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(aud_cntl_st, tmp);
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intel_de_write(dev_priv, aud_cntl_st, tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min(drm_eld_size(eld), 84);
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for (i = 0; i < len / 4; i++)
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I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
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intel_de_write(dev_priv, hdmiw_hdmiedid,
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*((const u32 *)eld + i));
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/* ELD valid */
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tmp = I915_READ(aud_cntrl_st2);
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tmp = intel_de_read(dev_priv, aud_cntrl_st2);
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tmp |= eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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intel_de_write(dev_priv, aud_cntrl_st2, tmp);
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/* Enable timestamps */
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tmp = I915_READ(aud_config);
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tmp = intel_de_read(dev_priv, aud_config);
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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@ -679,7 +682,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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else
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tmp |= audio_config_hdmi_pixel_clock(crtc_state);
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I915_WRITE(aud_config, tmp);
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intel_de_write(dev_priv, aud_config, tmp);
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}
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/**
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@ -856,7 +859,8 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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if (dev_priv->audio_power_refcount++ == 0) {
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if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
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I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
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intel_de_write(dev_priv, AUD_FREQ_CNTRL,
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dev_priv->audio_freq_cntrl);
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drm_dbg_kms(&dev_priv->drm,
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"restored AUD_FREQ_CNTRL to 0x%x\n",
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dev_priv->audio_freq_cntrl);
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@ -867,9 +871,8 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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glk_force_audio_cdclk(dev_priv, true);
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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I915_WRITE(AUD_PIN_BUF_CTL,
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(I915_READ(AUD_PIN_BUF_CTL) |
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AUD_PIN_BUF_ENABLE));
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intel_de_write(dev_priv, AUD_PIN_BUF_CTL,
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(intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE));
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}
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return ret;
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@ -904,15 +907,15 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
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* Enable/disable generating the codec wake signal, overriding the
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* internal logic to generate the codec wake to controller.
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*/
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tmp = I915_READ(HSW_AUD_CHICKENBIT);
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tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
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tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
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I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
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intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
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usleep_range(1000, 1500);
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if (enable) {
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tmp = I915_READ(HSW_AUD_CHICKENBIT);
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tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT);
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tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
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I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
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intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp);
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usleep_range(1000, 1500);
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}
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@ -1135,7 +1138,8 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
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}
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if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
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dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
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dev_priv->audio_freq_cntrl = intel_de_read(dev_priv,
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AUD_FREQ_CNTRL);
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drm_dbg_kms(&dev_priv->drm,
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"init value of AUD_FREQ_CNTRL of 0x%x\n",
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dev_priv->audio_freq_cntrl);
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