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sh_eth: add sh_eth_cpu_data::cexcr flag

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GEther controllers have CERCR/CEECR instead of CNDCR on the others.
Currently we are calling sh_eth_is_gether() in order to check for this,
however it would be simpler  to check the new 'cexcr' bitfield in the
'struct sh_eth_cpu_data';  then we'd be able to remove sh_eth_is_gether()
as there would be no callers left...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sergei Shtylyov 2018-03-24 23:12:54 +03:00 • committed by David S. Miller
parent ce9134dff6
commit 4c1d45850d
2 changed files with 6 additions and 6 deletions
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11
drivers/net/ethernet/renesas/sh_eth.c
View file

@ -450,11 +450,6 @@ static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
} }
static bool sh_eth_is_gether(struct sh_eth_private *mdp)
{
return mdp->reg_offset == sh_eth_offset_gigabit;
}
static void sh_eth_select_mii(struct net_device *ndev) static void sh_eth_select_mii(struct net_device *ndev)
{ {
struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_private *mdp = netdev_priv(ndev);
@ -661,6 +656,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
.tsu = 1, .tsu = 1,
.select_mii = 1, .select_mii = 1,
.magic = 1, .magic = 1,
.cexcr = 1,
}; };
/* There is CPU dependent code */ /* There is CPU dependent code */
@ -918,6 +914,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
.no_ade = 1, .no_ade = 1,
.xdfar_rw = 1, .xdfar_rw = 1,
.tsu = 1, .tsu = 1,
.cexcr = 1,
.dual_port = 1, .dual_port = 1,
}; };
@ -959,6 +956,7 @@ static struct sh_eth_cpu_data sh7734_data = {
.hw_checksum = 1, .hw_checksum = 1,
.select_mii = 1, .select_mii = 1,
.magic = 1, .magic = 1,
.cexcr = 1,
}; };
/* SH7763 */ /* SH7763 */
@ -997,6 +995,7 @@ static struct sh_eth_cpu_data sh7763_data = {
.tsu = 1, .tsu = 1,
.irq_flags = IRQF_SHARED, .irq_flags = IRQF_SHARED,
.magic = 1, .magic = 1,
.cexcr = 1,
.dual_port = 1, .dual_port = 1,
}; };
@ -2540,7 +2539,7 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
if (sh_eth_is_gether(mdp)) { if (mdp->cd->cexcr) {
sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
CERCR); CERCR);
sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,

1
drivers/net/ethernet/renesas/sh_eth.h
View file

@ -515,6 +515,7 @@ struct sh_eth_cpu_data {
unsigned rtrate:1; /* EtherC has RTRATE register */ unsigned rtrate:1; /* EtherC has RTRATE register */
unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */ unsigned magic:1; /* EtherC has ECMR.MPDE and ECSR.MPD */
unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */ unsigned no_tx_cntrs:1; /* EtherC DOES NOT have TX error counters */
unsigned cexcr:1; /* EtherC has CERCR/CEECR */
unsigned dual_port:1; /* Dual EtherC/E-DMAC */ unsigned dual_port:1; /* Dual EtherC/E-DMAC */
}; };