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Merge branch 'CR_1843_515_I2S_vol_Xingyu.Wu' into 'jh7110-5.15.y-devel'

Browse source 
CR_1843 515 i2 s vol xingyu.wu

See merge request sdk/linux!400
This commit is contained in:
andy.hu 2022-08-19 08:09:26 +00:00
commit 4c5966a0c9
5 changed files with 30 additions and 36 deletions
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6
arch/riscv/boot/dts/starfive/jh7110-clk.dtsi Normal file → Executable file
View file

@ -76,12 +76,6 @@
clock-frequency = <50000000>;
};
stg_apb: stg_apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <51200000>;
};
gmac0_rmii_refin: gmac0_rmii_refin {
compatible = "fixed-clock";
#clock-cells = <0>;

4
arch/riscv/boot/dts/starfive/jh7110.dtsi
View file

@ -332,7 +332,7 @@
<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
<&tdm_ext>, <&mclk_ext>,
<&jtag_tck_inner>, <&bist_apb>,
<&stg_apb>, <&clk_rtc>,
<&clk_rtc>,
<&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
clock-names = "osc", "gmac1_rmii_refin",
"gmac1_rgmii_rxin",
@ -340,7 +340,7 @@
"i2srx_bclk_ext", "i2srx_lrck_ext",
"tdm_ext", "mclk_ext",
"jtag_tck_inner", "bist_apb",
"stg_apb", "clk_rtc",
"clk_rtc",
"gmac0_rmii_refin", "gmac0_rgmii_rxin";
#clock-cells = <1>;
starfive,sys-syscon = <&sys_syscon 0x18 0x1c

11
drivers/clk/starfive/clk-starfive-jh7110-stg.c
View file

@ -15,8 +15,6 @@
/* external clocks */
#define JH7110_OSC (JH7110_CLK_END + 0)
/* stg external clocks */
#define JH7110_STG_APB (JH7110_CLK_END + 11)
static const struct jh7110_clk_data jh7110_clk_stg_data[] __initconst = {
//hifi4
@ -127,6 +125,9 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,
priv->pll[PLL_OF(JH7110_STG_SYSCON_PCLK)] =
devm_clk_hw_register_fixed_factor(priv->dev,
"u0_stg_syscon_pclk", "stg_apb", 0, 1, 1);
priv->pll[PLL_OF(JH7110_STG_APB)] =
devm_clk_hw_register_fixed_factor(priv->dev,
"stg_apb", "apb_bus", 0, 1, 1);
for (idx = JH7110_CLK_SYS_REG_END; idx < JH7110_CLK_STG_REG_END; idx++) {
u32 max = jh7110_clk_stg_data[idx].max;
@ -145,15 +146,13 @@ int __init clk_starfive_jh7110_stg_init(struct platform_device *pdev,
for (i = 0; i < init.num_parents; i++) {
unsigned int pidx = jh7110_clk_stg_data[idx].parents[i];
if (pidx < JH7110_CLK_STG_REG_END)
if (pidx < JH7110_CLK_REG_END )
parents[i].hw = &priv->reg[pidx].hw;
else if ((pidx < JH7110_CLK_STG_END) &&
(pidx > JH7110_CLK_SYS_END))
(pidx > (JH7110_CLK_SYS_END - 1)))
parents[i].hw = priv->pll[PLL_OF(pidx)];
else if (pidx == JH7110_OSC)
parents[i].fw_name = "osc";
else if (pidx == JH7110_STG_APB)
parents[i].fw_name = "stg_apb";
}
clk->hw.init = &init;

29
include/dt-bindings/clock/starfive-jh7110-clkgen.h
View file

@ -350,24 +350,25 @@
#define JH7110_E2_IRQ_SYNC_CLK_CORE 324
#define JH7110_STG_CRG_PCLK 325
#define JH7110_STG_SYSCON_PCLK 326
#define JH7110_STG_APB 327
#define JH7110_CLK_STG_END 327
#define JH7110_CLK_STG_END 328
/* aon other */
#define JH7110_U0_GMAC5_CLK_PTP 327
#define JH7110_U0_GMAC5_CLK_RMII 328
#define JH7110_AON_SYSCON_PCLK 329
#define JH7110_AON_IOMUX_PCLK 330
#define JH7110_AON_CRG_PCLK 331
#define JH7110_PMU_CLK_APB 332
#define JH7110_PMU_CLK_WKUP 333
#define JH7110_RTC_HMS_CLK_OSC32K_G 334
#define JH7110_32K_OUT 335
#define JH7110_RESET0_CTRL_CLK_SRC 336
#define JH7110_U0_GMAC5_CLK_PTP 328
#define JH7110_U0_GMAC5_CLK_RMII 329
#define JH7110_AON_SYSCON_PCLK 330
#define JH7110_AON_IOMUX_PCLK 331
#define JH7110_AON_CRG_PCLK 332
#define JH7110_PMU_CLK_APB 333
#define JH7110_PMU_CLK_WKUP 334
#define JH7110_RTC_HMS_CLK_OSC32K_G 335
#define JH7110_32K_OUT 336
#define JH7110_RESET0_CTRL_CLK_SRC 337
/* aon other and source */
#define JH7110_PCLK_MUX_FUNC_PCLK 337
#define JH7110_PCLK_MUX_BIST_PCLK 338
#define JH7110_PCLK_MUX_FUNC_PCLK 338
#define JH7110_PCLK_MUX_BIST_PCLK 339
#define JH7110_CLK_END 339
#define JH7110_CLK_END 340
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */

16
sound/soc/codecs/wm8960.c
View file

@ -930,27 +930,27 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
snd_soc_component_write(component, WM8960_POWER2, 0x1f9);
} else if (audio_format == 0x2) {//I2S Format
if (!tx) {
snd_soc_component_update_bits(component, WM8960_LINVOL, 0x3<<7, 0x2<<7);
snd_soc_component_update_bits(component, WM8960_RINVOL, 0x3<<7, 0x2<<7);
snd_soc_component_update_bits(component, WM8960_LINVOL, 0x1<<7, 0x1<<7);
snd_soc_component_update_bits(component, WM8960_RINVOL, 0x1<<7, 0x1<<7);
snd_soc_component_write(component, WM8960_CLOCK1, 0x00); //0xd8
snd_soc_component_write(component, WM8960_ALC1, 0x1bb);
snd_soc_component_write(component, WM8960_ALC2, 0x30);
snd_soc_component_write(component, WM8960_ALC3, 0x30);
snd_soc_component_write(component, WM8960_NOISEG, 0xf9);
snd_soc_component_write(component, WM8960_LADC, 0x197);
snd_soc_component_write(component, WM8960_RADC, 0x197);
snd_soc_component_write(component, WM8960_ADDCTL1, 0xc0);
snd_soc_component_write(component, WM8960_ADDCTL3, 0x03);
snd_soc_component_write(component, WM8960_LOUT2, 0x1ff);
snd_soc_component_write(component, WM8960_ROUT2, 0x1ff);
snd_soc_component_write(component, WM8960_BYPASS1, 0x00);
snd_soc_component_write(component, WM8960_BYPASS2, 0x00);
snd_soc_component_write(component, WM8960_ADDCTL4, 0x00);
} else {
if (params_channels(params) == 1)
snd_soc_component_write(component, WM8960_LOUT1, 0x100);
else
snd_soc_component_update_bits(component, WM8960_LOUT1, 0x170, 0x170);
else {
if (snd_soc_component_read(component, WM8960_LOUT1) & 0x7f)
snd_soc_component_update_bits(component, WM8960_LOUT1, 0x100, 0x100);
else
snd_soc_component_write(component, WM8960_LOUT1, 0x170);
}
}
}