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clk: si5351: Add DT property to enable PLL reset

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Add optional output clock DT property to enable PLL reset when a clock
output is enabled.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Sergej Sawazki 2017-09-16 13:44:41 +02:00 • committed by Stephen Boyd
parent 758231d5a8
commit 51279ef9f6
3 changed files with 6 additions and 0 deletions
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2
include/linux/platform_data/si5351.h
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@ -86,6 +86,7 @@ enum si5351_disable_state {
* @multisynth_src: multisynth source clock
* @clkout_src: clkout source clock
* @pll_master: if true, clkout can also change pll rate
* @pll_reset: if true, clkout can reset its pll
* @drive: output drive strength
* @rate: initial clkout rate, or default if 0
*/
@ -95,6 +96,7 @@ struct si5351_clkout_config {
enum si5351_drive_strength drive;
enum si5351_disable_state disable_state;
bool pll_master;
bool pll_reset;
unsigned long rate;
};