mirror of
https://github.com/Fishwaldo/Star64_linux.git
synced 2025-03-16 12:14:06 +00:00
riscv: dts: Add JH7100 and BeagleV Starlight support
Based on the device tree in https://github.com/starfive-tech/u-boot/ with contributions from: yanhong.wang <yanhong.wang@starfivetech.com> Huan.Feng <huan.feng@starfivetech.com> ke.zhu <ke.zhu@starfivetech.com> yiming.li <yiming.li@starfivetech.com> jack.zhu <jack.zhu@starfivetech.com> Samin Guo <samin.guo@starfivetech.com> Chenjieqin <Jessica.Chen@starfivetech.com> bo.li <bo.li@starfivetech.com> Rearranged, cleanups, fixes and TPS65086 added by Emil. Cleanups, fixes and LED added by Geert. Cleanups and GPIO fixes from Drew. Thermal zone added by Stephen. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org> Signed-off-by: Drew Fustini <drew@beagleboard.org>
This commit is contained in:
TekkamanV
Emil Renner Berthing
parent
66a1c63c40
commit
56a41a1459
4 changed files with 1041 additions and 1 deletions
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += sifive
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subdir-y += sifive starfive
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subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
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subdir-y += microchip
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2
arch/riscv/boot/dts/starfive/Makefile
Normal file
2
arch/riscv/boot/dts/starfive/Makefile
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_STARFIVE_VIC7100) += jh7100-beaglev-starlight.dtb
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439
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
Normal file
439
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
Normal file
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@ -0,0 +1,439 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
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/dts-v1/;
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#include "jh7100.dtsi"
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#include <dt-bindings/starfive_fb.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "BeagleV Starlight Beta";
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compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100";
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aliases {
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mshc0 = &sdio0;
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mshc1 = &sdio1;
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serial0 = &uart3;
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serial1 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <6250000>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x0>;
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};
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leds {
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compatible = "gpio-leds";
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led-ack {
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gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_HEARTBEAT;
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linux,default-trigger = "heartbeat";
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label = "ack";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x28000000>;
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alignment = <0x0 0x1000>;
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alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
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linux,cma-default;
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};
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jpu_reserved: framebuffer@c9000000 {
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reg = <0x0 0xc9000000 0x0 0x4000000>;
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};
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nvdla_reserved: framebuffer@d0000000 {
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reg = <0x0 0xd0000000 0x0 0x28000000>;
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};
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vin_reserved: framebuffer@f9000000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0xf9000000 0x0 0x1000000>;
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};
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sffb_reserved: framebuffer@fb000000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0xfb000000 0x0 0x2000000>;
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};
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};
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wifi_pwrseq: wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c0 {
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imx219@10 {
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compatible = "imx219";
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reg = <0x10>;
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reset-gpio = <&gpio 58 0>;
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};
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tps65086@5e {
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compatible = "ti,tps65086";
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reg = <0x5e>;
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/*
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interrupt-parent = <&gpio1>;
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interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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*/
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gpio-controller;
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#gpio-cells = <2>;
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};
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tda998x@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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};
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};
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&i2c2 {
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seeed_plane_i2c@45 {
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compatible = "seeed_panel";
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reg = <0x45>;
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};
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};
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&osc0_clk {
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clock-frequency = <25000000>;
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};
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&osc1_clk {
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clock-frequency = <27000000>;
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};
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&qspi {
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nor_flash: nor-flash@0 {
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compatible = "spi-flash";
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reg = <0>;
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spi-max-frequency = <31250000>;
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page-size = <256>;
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block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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nand_flash: nand-flash@1 {
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compatible = "spi-flash-nand";
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reg = <1>;
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spi-max-frequency = <31250000>;
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page-size = <2048>;
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block-size = <17>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&sdio0 {
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broken-cd;
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <10000000>;
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status = "okay";
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};
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&sdio1 {
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-sdio-irq;
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cap-power-off-card;
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max-frequency = <10000000>;
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mmc-pwrseq = <&wifi_pwrseq>;
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non-removable;
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status = "okay";
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wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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&sfivefb {
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/*
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pp1 {
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pp-id = <1>;
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fifo-out;
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src-format = <COLOR_YUV420_NV21>;
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src-width = <800>;
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src-height = <480>;
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dst-format = <COLOR_RGB888_ARGB>;
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dst-width = <800>;
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dst-height = <480>;
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};
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*/
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tda_998x_1080p {
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compatible = "starfive,display-dev";
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panel_name = "tda_998x_1080p";
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panel_lcd_id = <22>; /* 1080p */
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interface_info = "rgb_interface";
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refresh_en = <1>;
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bits-per-pixel = <16>;
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physical-width = <62>;
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physical-height = <114>;
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panel-width = <1920>;
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panel-height = <1080>;
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pixel-clock = <78000000>;
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/*dyn_fps;*/ /*dynamic frame rate support*/
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/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
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/*gamma-command-monolithic;*/
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/*ce-command-monolithic;*/
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/*resume-with-gamma;*/
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/*resume-with-ce;*/
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/*mipi info*/
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mipi-byte-clock = <78000>;
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mipi-escape-clock = <13000>;
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lane-no = <4>;
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display_mode = "video_mode"; /*video_mode, command_mode*/
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/*
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auto_stop_clklane_en;
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im_pin_val;*/
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color_bits = <COLOR_CODE_24BIT>;
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/*is_18bit_loosely;*/
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/*video mode info*/
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h-pulse-width = <44>;
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h-back-porch = <148>;
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h-front-porch = <88>;
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v-pulse-width = <5>;
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v-back-porch = <36>;
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v-front-porch = <4>;
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status = "okay";
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sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
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lp_cmd_en;
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/*lp_hfp_en;*/
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/*lp_hbp_en;*/
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/*lp_vact_en;*/
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lp_vfp_en;
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lp_vbp_en;
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lp_vsa_en;
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traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
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/*phy info*/
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data_tprepare = /bits/ 8 <0>;
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data_hs_zero = /bits/ 8 <0>;
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data_hs_exit = /bits/ 8 <0>;
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data_hs_trail = /bits/ 8 <0>;
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/*te info*/
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te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
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te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
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te_enable = <0>;
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cm_te_effect_sync_enable = <0>; /*used in command mode*/
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te_count_per_sec = <64>; /*used in esd*/
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/*ext info*/
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/*
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crc_rx_en;
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ecc_rx_en;
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eotp_rx_en;
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*/
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eotp_tx_en;
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dev_read_time = <0x7fff>;
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/*type cmd return_count return_code*/
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/*id_read_cmd_info = [];*/
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/*pre_id_cmd = [];*/
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/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
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/*pre_esd_cmd = [];*/
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/*panel-on-command = [];*/
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/*panel-off-command = [];*/
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/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
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/*
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panel-gamma-warm-command = [
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];
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panel-gamma-nature-command = [
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];
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panel-gamma-cool-command = [
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];
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panel-ce-std-command = [
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];
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panel-ce-vivid-command = [
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];
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*/
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};
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seeed_5_inch {
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compatible = "starfive,display-dev";
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panel_name = "seeed_5_inch";
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panel_lcd_id = <22>; /* 480p */
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interface_info = "mipi_interface";
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refresh_en = <1>;
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bits-per-pixel = <24>;
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physical-width = <62>;
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physical-height = <114>;
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panel-width = <800>;
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panel-height = <480>;
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pixel-clock = <27500000>;
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/*dyn_fps;*/ /*dynamic frame rate support*/
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fps = <50>;
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/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
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/*gamma-command-monolithic;*/
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/*ce-command-monolithic;*/
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/*resume-with-gamma;*/
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/*resume-with-ce;*/
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/*mipi info*/
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mipi-byte-clock = <78000>;
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mipi-escape-clock = <13000>;
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lane-no = <1>;
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display_mode = "video_mode"; /*video_mode, command_mode*/
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/*
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auto_stop_clklane_en;
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im_pin_val;
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*/
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color_bits = <COLOR_CODE_24BIT>;
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/*is_18bit_loosely;*/
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/*video mode info*/
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h-pulse-width = <10>;
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h-back-porch = <20>;
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h-front-porch = <50>;
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v-pulse-width = <5>;
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v-back-porch = <5>;
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v-front-porch = <135>;
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/*seeed panel mode info*/
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dphy_bps = <700000000>;
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dsi_burst_mode = <0>;
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dsi_sync_pulse = <1>;
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// bytes
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dsi_hsa = <30>;
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dsi_hbp = <211>;
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dsi_hfp = <159>;
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// lines
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dsi_vsa = <5>;
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dsi_vbp = <5>;
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dsi_vfp = <134>;
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status = "okay";
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sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
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lp_cmd_en;
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/*lp_hfp_en;*/
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/*lp_hbp_en;*/
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/*lp_vact_en;*/
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lp_vfp_en;
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lp_vbp_en;
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lp_vsa_en;
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traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
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/*phy info*/
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data_tprepare = /bits/ 8 <0>;
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data_hs_zero = /bits/ 8 <0>;
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data_hs_exit = /bits/ 8 <0>;
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data_hs_trail = /bits/ 8 <0>;
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/*te info*/
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te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
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te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
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te_enable = <0>;
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cm_te_effect_sync_enable = <0>; /*used in command mode*/
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te_count_per_sec = <64>; /*used in esd*/
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/*ext info*/
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/*
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crc_rx_en;
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ecc_rx_en;
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eotp_rx_en;
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*/
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eotp_tx_en;
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dev_read_time = <0x7fff>;
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/*type cmd return_count return_code*/
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/*id_read_cmd_info = [];*/
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/*pre_id_cmd = [];*/
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/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
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/*pre_esd_cmd = [];*/
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/*panel-on-command = [];*/
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/*panel-off-command = [];*/
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/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
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/*
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panel-gamma-warm-command = [
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];
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panel-gamma-nature-command = [
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];
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panel-gamma-cool-command = [
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];
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panel-ce-std-command = [
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];
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panel-ce-vivid-command = [
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];
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*/
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};
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};
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&spi2 {
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status = "okay";
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spi_dev0: spi@0 {
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compatible = "rohm,dh2228fv";
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spi-max-frequency = <10000000>;
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reg = <0>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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&usb3 {
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dr_mode = "host";
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status = "okay";
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};
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599
arch/riscv/boot/dts/starfive/jh7100.dtsi
Normal file
599
arch/riscv/boot/dts/starfive/jh7100.dtsi
Normal file
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@ -0,0 +1,599 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
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/dts-v1/;
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#include <dt-bindings/clock/starfive-jh7100-clkgen.h>
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#include <dt-bindings/starfive_fb.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <2>;
|
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#size-cells = <2>;
|
||||
compatible = "starfive,jh7100";
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|
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cpus {
|
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#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
cpu@0 {
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||||
compatible = "sifive,u74-mc", "riscv";
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||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
starfive,itim = <&itim0>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
reg = <1>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
starfive,itim = <&itim1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
cpu1_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
osc0_clk: osc0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc1_clk: osc1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "starfive,jh7100", "simple-bus";
|
||||
interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ccache: cache-controller@2010000 {
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-sets = <2048>;
|
||||
cache-size = <2097152>;
|
||||
cache-unified;
|
||||
compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
|
||||
interrupts = <128 131 129 130>;
|
||||
/*next-level-cache = <&L40 &L36>;*/
|
||||
reg = <0x0 0x2010000 0x0 0x1000>,
|
||||
<0x0 0x8000000 0x0 0x2000000>;
|
||||
reg-names = "control", "sideband";
|
||||
};
|
||||
|
||||
dtim: dtim@1000000 {
|
||||
compatible = "starfive,dtim0";
|
||||
reg = <0x0 0x1000000 0x0 0x2000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
itim0: itim@1808000 {
|
||||
compatible = "starfive,itim0";
|
||||
reg = <0x0 0x1808000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
itim1: itim@1820000 {
|
||||
compatible = "starfive,itim0";
|
||||
reg = <0x0 0x1820000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
clint: clint@2000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,clint0";
|
||||
interrupts-extended = <&cpu0_intc 3>,
|
||||
<&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>,
|
||||
<&cpu1_intc 7>;
|
||||
reg = <0x0 0x2000000 0x0 0x10000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
plic: interrupt-controller@c000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,plic0";
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&cpu0_intc 11>,
|
||||
<&cpu0_intc 9>,
|
||||
<&cpu1_intc 11>,
|
||||
<&cpu1_intc 9>;
|
||||
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||||
reg-names = "control";
|
||||
riscv,max-priority = <7>;
|
||||
riscv,ndev = <127>;
|
||||
};
|
||||
|
||||
clkgen: clock-controller@11800000 {
|
||||
compatible = "starfive,jh7100-clkgen";
|
||||
reg = <0x0 0x11800000 0x0 0x10000>;
|
||||
clocks = <&osc0_clk>, <&osc1_clk>;
|
||||
clock-names = "osc0", "osc1";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@11870000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <92>;
|
||||
reg = <0x0 0x11870000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_HS_UART>,
|
||||
<&clkgen JH7100_CLK_APB1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <74250000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11880000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <93>;
|
||||
reg = <0x0 0x11880000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_HS_UART>,
|
||||
<&clkgen JH7100_CLK_APB1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <74250000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@12430000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <72>;
|
||||
reg = <0x0 0x12430000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART>,
|
||||
<&clkgen JH7100_CLK_APB2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <100000000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12440000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <73>;
|
||||
reg = <0x0 0x12440000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART>,
|
||||
<&clkgen JH7100_CLK_APB2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <100000000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma2p: dma-controller@100b0000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0x0 0x100b0000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_AXI>,
|
||||
<&clkgen JH7100_CLK_AHB0>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
interrupts = <2>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
snps,dma-masters = <1>;
|
||||
snps,data-width = <4>;
|
||||
snps,block-size = <4096 4096 4096 4096>;
|
||||
snps,priority = <0 1 2 3>;
|
||||
snps,axi-max-burst-len = <128>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dma1p: dma-controller@10500000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0x0 0x10500000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_AXI>,
|
||||
<&clkgen JH7100_CLK_AHB0>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
interrupts = <1>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
snps,dma-masters = <1>;
|
||||
snps,data-width = <3>;
|
||||
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
|
||||
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
snps,axi-max-burst-len = <64>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb@104c0000 {
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
|
||||
<0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
|
||||
<0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
|
||||
reg-names = "otg", "xhci", "dev";
|
||||
interrupts = <44>, <52>, <43>;
|
||||
interrupt-names = "host", "peripheral", "otg";
|
||||
phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
|
||||
maximum-speed = "super-speed";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio@11910000 {
|
||||
compatible = "starfive,jh7100-gpio";
|
||||
reg = <0x0 0x11910000 0x0 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
|
||||
i2c0: i2c@118b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x118b0000 0x0 0x10000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C0>;
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
scl-gpio = <&gpio 62 0>;
|
||||
sda-gpio = <&gpio 61 0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@118c0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x118c0000 0x0 0x10000>;
|
||||
interrupts = <97>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C0>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <100>;
|
||||
scl-gpio = <&gpio 47 0>;
|
||||
sda-gpio = <&gpio 48 0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@12450000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12450000 0x0 0x10000>;
|
||||
interrupts = <74>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C2>;
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
scl-gpio = <&gpio 60 0>;
|
||||
sda-gpio = <&gpio 59 0>;
|
||||
};
|
||||
|
||||
trng: trng@118d0000 {
|
||||
compatible = "starfive,vic-rng";
|
||||
reg = <0x0 0x118d0000 0x0 0x10000>;
|
||||
interrupts = <98>;
|
||||
clocks = <&clkgen JH7100_CLK_HF>;
|
||||
};
|
||||
|
||||
crypto: crypto@100d0000 {
|
||||
compatible = "starfive,vic-sec";
|
||||
reg = <0x0 0x100d0000 0x0 0x20000>,
|
||||
<0x0 0x11800234 0x0 0xc>;
|
||||
reg-names = "secmem", "secclk";
|
||||
interrupts = <31>;
|
||||
clocks = <&clkgen JH7100_CLK_HF>;
|
||||
};
|
||||
|
||||
/* gmac device configuration */
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <256 128 64 32 0 0 0>;
|
||||
};
|
||||
|
||||
gmac: ethernet@10020000 {
|
||||
compatible = "snps,dwmac";
|
||||
reg = <0x0 0x10020000 0x0 0x10000>;
|
||||
interrupts = <6 7>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
max-frame-size = <9000>;
|
||||
phy-mode = "rgmii-txid";
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <32768>;
|
||||
tx-fifo-depth = <16384>;
|
||||
clocks = <&clkgen JH7100_CLK_GMAC>;
|
||||
clock-names = "stmmaceth";
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8 = <1>;
|
||||
/*snps,force_sf_dma_mode;*/
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
};
|
||||
|
||||
nbdla: nvdla@11940000 {
|
||||
compatible = "nvidia,nvdla_os_initial";
|
||||
interrupts = <22>;
|
||||
memory-region = <&nvdla_reserved>;
|
||||
reg = <0x0 0x11940000 0x0 0x40000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
jpu: coadj12@11900000 {
|
||||
compatible = "cm,codaj12-jpu-1";
|
||||
reg = <0x0 0x11900000 0x0 0x300>;
|
||||
memory-region = <&jpu_reserved>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clkgen JH7100_CLK_JPU>;
|
||||
clock-names = "jpege";
|
||||
reg-names = "control";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vpu_dec: vpu_dec@118f0000 {
|
||||
compatible = "c&m,cm511-vpu";
|
||||
reg = <0 0x118f0000 0 0x10000>;
|
||||
//memory-region = <&vpu_reserved>;
|
||||
interrupts = <23>;
|
||||
clocks = <&clkgen JH7100_CLK_VPU>;
|
||||
clock-names = "vcodec";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vpu_enc: vpu_enc@118e0000 {
|
||||
compatible = "cm,cm521-vpu";
|
||||
reg = <0x0 0x118e0000 0x0 0x4000>;
|
||||
interrupts = <26>;
|
||||
clocks = <&clkgen JH7100_CLK_VPU>;
|
||||
clock-names = "vcodec";
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ptc: pwm@12490000 {
|
||||
compatible = "starfive,pwm0";
|
||||
reg = <0x0 0x12490000 0x0 0x10000>;
|
||||
reg-names = "control";
|
||||
sifive,approx-period = <100000000>;
|
||||
clocks = <&clkgen JH7100_CLK_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
sifive,npwm = <8>;
|
||||
|
||||
};
|
||||
|
||||
qspi: spi@11860000 {
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x11860000 0x0 0x10000>,
|
||||
<0x0 0x20000000 0x0 0x20000000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clkgen JH7100_CLK_QSPI>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
status = "disabled";
|
||||
spi-max-frequency = <250000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
spi0: spi@11890000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <FIXME>;
|
||||
reg = <0x0 0x11890000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@118a0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <FIXME>;
|
||||
reg = <0x0 0x118a0000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI>;
|
||||
status = "disabled";
|
||||
};
|
||||
*/
|
||||
|
||||
spi2: spi@12410000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
reg = <0x0 0x12410000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xrp@f0000000 {
|
||||
compatible = "cdns,xrp";
|
||||
reg = <0x0 0xf0000000 0x0 0x01ffffff>,
|
||||
<0x10 0x72000000 0x0 0x00001000>,
|
||||
<0x10 0x72001000 0x0 0x00fff000>,
|
||||
<0x0 0x124b0000 0x0 0x00010000>;
|
||||
clocks = <&clkgen JH7100_CLK_HF>;
|
||||
firmware-name = "vp6_elf";
|
||||
dsp-irq = <19 20>;
|
||||
dsp-irq-src = <0x20 0x21>;
|
||||
intc-irq-mode = <1>;
|
||||
intc-irq = <0 1>;
|
||||
interrupts = <27 28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x0 0x40000000 0x01000000>,
|
||||
<0xb0000000 0x10 0x70000000 0x3000000>;
|
||||
dsp@0 {
|
||||
};
|
||||
};
|
||||
|
||||
sdio0: mmc@10000000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
reg = <0x0 0x10000000 0x0 0x10000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clkgen JH7100_CLK_DWMMC_BIU>;
|
||||
clock-names = "biu";
|
||||
clock-frequency = <100000000>;
|
||||
data-addr = <0>;
|
||||
fifo-depth = <32>;
|
||||
fifo-watermark-aligned;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@10010000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
reg = <0x0 0x10010000 0x0 0x10000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&clkgen JH7100_CLK_DWMMC_BIU>;
|
||||
clock-names = "biu";
|
||||
clock-frequency = <100000000>;
|
||||
data-addr = <0>;
|
||||
fifo-depth = <32>;
|
||||
fifo-watermark-aligned;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfivefb: sfivefb@12000000 {
|
||||
compatible = "starfive,vpp-lcdc";
|
||||
interrupts = <101>, <103>;
|
||||
interrupt-names = "lcdc_irq", "vpp1_irq";
|
||||
reg = <0x0 0x12000000 0x0 0x10000>,
|
||||
<0x0 0x12100000 0x0 0x10000>,
|
||||
<0x0 0x12040000 0x0 0x10000>,
|
||||
<0x0 0x12080000 0x0 0x10000>,
|
||||
<0x0 0x120c0000 0x0 0x10000>,
|
||||
<0x0 0x12240000 0x0 0x10000>,
|
||||
<0x0 0x12250000 0x0 0x10000>,
|
||||
<0x0 0x12260000 0x0 0x10000>;
|
||||
reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
|
||||
memory-region = <&sffb_reserved>;
|
||||
clocks = <&clkgen JH7100_CLK_UART>,
|
||||
<&clkgen JH7100_CLK_APB2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
status = "okay";
|
||||
ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
|
||||
};
|
||||
|
||||
vin_sysctl: vin_sysctl@19800000 {
|
||||
compatible = "starfive,stf-vin";
|
||||
reg = <0x0 0x19800000 0x0 0x10000>,
|
||||
<0x0 0x19810000 0x0 0x10000>,
|
||||
<0x0 0x19820000 0x0 0x10000>,
|
||||
<0x0 0x19830000 0x0 0x10000>,
|
||||
<0x0 0x19840000 0x0 0x10000>,
|
||||
<0x0 0x19870000 0x0 0x30000>,
|
||||
<0x0 0x198a0000 0x0 0x30000>,
|
||||
<0x0 0x11800000 0x0 0x10000>,
|
||||
<0x0 0x11840000 0x0 0x10000>,
|
||||
<0x0 0x11858000 0x0 0x10000>;
|
||||
reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
|
||||
"isp0", "isp1", "tclk", "trst", "iopad";
|
||||
interrupts = <119 109>;
|
||||
memory-region = <&vin_reserved>;
|
||||
/*defaule config for imx219 vin&isp*/
|
||||
format = <SRC_CSI2RX_VIN_ISP>;
|
||||
frame-width = <800>;
|
||||
frame-height =<480>;
|
||||
isp0_enable;
|
||||
csi-lane = <2>;
|
||||
csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
|
||||
csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
|
||||
csi-clane-swap = /bits/ 8 <0>;
|
||||
csi-clane-pn-swap = /bits/ 8 <0>;
|
||||
csi-mipiID = <0>;
|
||||
csi-width = <1920>;
|
||||
csi-height = <1080>;
|
||||
csi-dt = <0x2b>;
|
||||
};
|
||||
|
||||
sfctemp: tmon@124a0000 {
|
||||
compatible = "starfive,jh7100-temp";
|
||||
reg = <0x0 0x124a0000 0x0 0x10000>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
interrupts = <122>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <15000>;
|
||||
|
||||
thermal-sensors = <&sfctemp>;
|
||||
|
||||
cooling-maps {
|
||||
};
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu_alert0 {
|
||||
/* milliCelsius */
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit: cpu_crit {
|
||||
/* milliCelsius */
|
||||
temperature = <90000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
otp: otp@11810000 {
|
||||
compatible = "starfive,fu740-otp";
|
||||
reg = <0x0 0x11810000 0x0 0x10000>;
|
||||
fuse-count = <0x200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue