Merge tag 'JH7110_SDK_6.6_v1.3.0' into vf2-6.6.y-devel

drivers/clk/starfive/clk-starfive-jh7110-sys.c

@@ -385,6 +385,21 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
 }
 EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
 
+static int jh7110_syscrg_suspend(struct device *dev)
+{
+	return clk_save_context();
+}
+
+static int jh7110_syscrg_resume(struct device *dev)
+{
+	clk_restore_context();
+	return 0;
+}
+
+static const struct dev_pm_ops jh7110_syscrg_pm_ops = {
+	LATE_SYSTEM_SLEEP_PM_OPS(jh7110_syscrg_suspend, jh7110_syscrg_resume)
+};
+
 static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 {
 	struct jh71x0_clk_priv *priv;
@@ -558,6 +573,7 @@ static struct platform_driver jh7110_syscrg_driver = {
 	.driver = {
 		.name = "clk-starfive-jh7110-sys",
 		.of_match_table = jh7110_syscrg_match,
+		.pm = pm_sleep_ptr(&jh7110_syscrg_pm_ops),
 		.suppress_bind_attrs = true,
 	},
 };

drivers/clk/starfive/clk-starfive-jh71x0.c

@@ -10,6 +10,8 @@
 #include <linux/device.h>
 #include <linux/io.h>
 
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
 #include "clk-starfive-jh71x0.h"
 
 static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
@@ -70,6 +72,11 @@ static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
 	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
 	u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
 
+	if (clk->idx == JH7110_SYSCLK_UART3_CORE ||
+	    clk->idx == JH7110_SYSCLK_UART4_CORE ||
+	    clk->idx == JH7110_SYSCLK_UART5_CORE)
+		div >>= 8;
+
 	return div ? parent_rate / div : 0;
 }
 
@@ -110,6 +117,12 @@ static int jh71x0_clk_set_rate(struct clk_hw *hw,
 	unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
 				  1UL, (unsigned long)clk->max_div);
 
+	/* UART3-5: [15:8]: integer part of the divisor. [7:0] fraction part of the divisor */
+	if (clk->idx == JH7110_SYSCLK_UART3_CORE ||
+	    clk->idx == JH7110_SYSCLK_UART4_CORE ||
+	    clk->idx == JH7110_SYSCLK_UART5_CORE)
+		div <<= 8;
+
 	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
 	return 0;
 }
@@ -223,11 +236,95 @@ static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
 #define jh71x0_clk_debug_init NULL
 #endif
 
+#ifdef CONFIG_PM_SLEEP
+static int jh7110_clk_save_context(struct clk_hw *hw)
+{
+	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+	struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
+
+	if (!clk || !priv)
+		return 0;
+
+	spin_lock(&priv->rmw_lock);
+	clk->saved_reg = jh71x0_clk_reg_get(clk);
+	spin_unlock(&priv->rmw_lock);
+
+	return 0;
+}
+
+static void jh7110_clk_gate_restore_context(struct clk_hw *hw)
+{
+	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+
+	if (!clk)
+		return;
+
+	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, clk->saved_reg);
+}
+
+static void jh7110_clk_div_restore_context(struct clk_hw *hw)
+{
+	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+
+	if (!clk)
+		return;
+
+	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, clk->saved_reg);
+}
+
+static void jh7110_clk_mux_restore_context(struct clk_hw *hw)
+{
+	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+
+	if (!clk)
+		return;
+
+	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, clk->saved_reg);
+}
+
+static void jh7110_clk_inv_restore_context(struct clk_hw *hw)
+{
+	struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+
+	if (!clk)
+		return;
+
+	jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, clk->saved_reg);
+}
+
+static void jh7110_clk_gdiv_restore_context(struct clk_hw *hw)
+{
+	jh7110_clk_div_restore_context(hw);
+	jh7110_clk_gate_restore_context(hw);
+}
+
+static void jh7110_clk_gmux_restore_context(struct clk_hw *hw)
+{
+	jh7110_clk_mux_restore_context(hw);
+	jh7110_clk_gate_restore_context(hw);
+}
+
+static void jh7110_clk_mdiv_restore_context(struct clk_hw *hw)
+{
+	jh7110_clk_mux_restore_context(hw);
+	jh7110_clk_div_restore_context(hw);
+}
+
+static void jh7110_clk_gmd_restore_context(struct clk_hw *hw)
+{
+	jh7110_clk_mux_restore_context(hw);
+	jh7110_clk_div_restore_context(hw);
+	jh7110_clk_gate_restore_context(hw);
+}
+#endif
+
 static const struct clk_ops jh71x0_clk_gate_ops = {
 	.enable = jh71x0_clk_enable,
 	.disable = jh71x0_clk_disable,
 	.is_enabled = jh71x0_clk_is_enabled,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_gate_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_div_ops = {
@@ -235,6 +332,8 @@ static const struct clk_ops jh71x0_clk_div_ops = {
 	.determine_rate = jh71x0_clk_determine_rate,
 	.set_rate = jh71x0_clk_set_rate,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_div_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_fdiv_ops = {
@@ -252,6 +351,8 @@ static const struct clk_ops jh71x0_clk_gdiv_ops = {
 	.determine_rate = jh71x0_clk_determine_rate,
 	.set_rate = jh71x0_clk_set_rate,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_gdiv_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_mux_ops = {
@@ -259,6 +360,8 @@ static const struct clk_ops jh71x0_clk_mux_ops = {
 	.set_parent = jh71x0_clk_set_parent,
 	.get_parent = jh71x0_clk_get_parent,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_mux_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_gmux_ops = {
@@ -269,6 +372,8 @@ static const struct clk_ops jh71x0_clk_gmux_ops = {
 	.set_parent = jh71x0_clk_set_parent,
 	.get_parent = jh71x0_clk_get_parent,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_gmux_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_mdiv_ops = {
@@ -278,6 +383,8 @@ static const struct clk_ops jh71x0_clk_mdiv_ops = {
 	.set_parent = jh71x0_clk_set_parent,
 	.set_rate = jh71x0_clk_set_rate,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_mdiv_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_gmd_ops = {
@@ -290,12 +397,16 @@ static const struct clk_ops jh71x0_clk_gmd_ops = {
 	.set_parent = jh71x0_clk_set_parent,
 	.set_rate = jh71x0_clk_set_rate,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_gmd_restore_context),
 };
 
 static const struct clk_ops jh71x0_clk_inv_ops = {
 	.get_phase = jh71x0_clk_get_phase,
 	.set_phase = jh71x0_clk_set_phase,
 	.debug_init = jh71x0_clk_debug_init,
+	.save_context = pm_sleep_ptr(jh7110_clk_save_context),
+	.restore_context = pm_sleep_ptr(jh7110_clk_inv_restore_context),
 };
 
 const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)

drivers/clk/starfive/clk-starfive-jh71x0.h

@@ -107,6 +107,7 @@ struct jh71x0_clk {
 	struct clk_hw hw;
 	unsigned int idx;
 	unsigned int max_div;
+	u32 saved_reg;
 };
 
 struct jh71x0_clk_priv {

drivers/gpu/drm/verisilicon/Kconfig

@@ -4,6 +4,9 @@ config DRM_VERISILICON
 	tristate "DRM Support for VeriSilicon"
 	depends on DRM
 	select DRM_KMS_HELPER
+	select DRM_GEM_DMA_HELPER
+	select CMA
+	select DMA_CMA
 	help
 	  Choose this option if you have a VeriSilicon soc chipset.
 	  This driver provides VeriSilicon kernel mode

drivers/gpu/drm/verisilicon/vs_drv.c

@@ -27,6 +27,8 @@
 #endif
 #include <linux/of_reserved_mem.h>
 #include <drm/drm_aperture.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_gem_dma_helper.h>
 
 #include "vs_drv.h"
 #include "vs_fb.h"
@@ -52,17 +54,19 @@ extern struct platform_driver starfive_encoder_driver;
 static bool has_iommu = true;
 static struct platform_driver vs_drm_platform_driver;
 
-static const struct file_operations fops = {
-	.owner			= THIS_MODULE,
-	.open			= drm_open,
-	.release		= drm_release,
-	.unlocked_ioctl	= drm_ioctl,
-	.compat_ioctl	= drm_compat_ioctl,
-	.poll			= drm_poll,
-	.read			= drm_read,
-	.llseek			= noop_llseek,
-	.mmap			= drm_gem_mmap,
-};
+static int vs_drm_gem_dma_dumb_create(struct drm_file *file, struct drm_device *dev,
+			      struct drm_mode_create_dumb *args)
+{
+	struct vs_drm_private *priv = dev->dev_private;
+
+	unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+
+	args->pitch = ALIGN(pitch, priv->pitch_alignment);
+	return drm_gem_dma_dumb_create_internal(file, dev, args);
+}
+
+DEFINE_DRM_GEM_FOPS(vs_drm_fops);
+
 
 #ifdef CONFIG_DEBUG_FS
 static int vs_debugfs_planes_show(struct seq_file *s, void *data)
@@ -126,14 +130,13 @@ static int vs_debugfs_init(struct drm_minor *minor)
 
 static struct drm_driver vs_drm_driver = {
 	.driver_features	= DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM,
-	.lastclose		= drm_fb_helper_lastclose,
-	.gem_prime_import	= vs_gem_prime_import,
-	.gem_prime_import_sg_table = vs_gem_prime_import_sg_table,
-	.dumb_create		= vs_gem_dumb_create,
+
 #ifdef CONFIG_DEBUG_FS
 	.debugfs_init		= vs_debugfs_init,
 #endif
-	.fops			= &fops,
+	DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_drm_gem_dma_dumb_create),
+
+	.fops			= &vs_drm_fops,
 	.name			= DRV_NAME,
 	.desc			= DRV_DESC,
 	.date			= DRV_DATE,

drivers/gpu/drm/verisilicon/vs_plane.c

@@ -12,6 +12,7 @@
 #include <drm/drm_plane_helper.h>
 #include <drm/drm_fb_dma_helper.h>
 #include <drm/drm_gem_dma_helper.h>
+
 #include <drm/vs_drm.h>
 #include "vs_type.h"
 #include "vs_crtc.h"
@@ -289,10 +290,10 @@ static void vs_plane_atomic_update(struct drm_plane *plane,
 	num_planes = vs_get_plane_number(fb);
 
 	for (i = 0; i < num_planes; i++) {
-		struct vs_gem_object *vs_obj;
+		dma_addr_t dma_addr;
 
-		vs_obj = vs_fb_get_gem_obj(fb, i);
-		vs_plane->dma_addr[i] = vs_obj->iova + fb->offsets[i];
+		dma_addr = drm_fb_dma_get_gem_addr(new_state->fb, new_state, i);
+		vs_plane->dma_addr[i] = dma_addr;
 	}
 
 	plane_state->status.src = drm_plane_state_src(new_state);
@@ -318,8 +319,6 @@ static void vs_cursor_plane_atomic_update(struct drm_plane *plane,
 {
 	 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 										plane);
-	 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
-										plane);
 	 unsigned char i, num_planes;
 	 struct drm_framebuffer *fb;
 	 struct vs_plane *vs_plane = to_vs_plane(plane);
@@ -335,10 +334,10 @@ static void vs_cursor_plane_atomic_update(struct drm_plane *plane,
 	 num_planes = vs_get_plane_number(fb);
 
 	 for (i = 0; i < num_planes; i++) {
-		 struct vs_gem_object *vs_obj;
+		 dma_addr_t dma_addr;
 
-		 vs_obj = vs_fb_get_gem_obj(fb, i);
-		 vs_plane->dma_addr[i] = vs_obj->iova + fb->offsets[i];
+		 dma_addr = drm_fb_dma_get_gem_addr(new_state->fb, new_state, i);
+		 vs_plane->dma_addr[i] = dma_addr;
 	 }
 
 	 plane_state->status.src = drm_plane_state_src(new_state);
@@ -365,12 +364,11 @@ static int vs_cursor_plane_atomic_check(struct drm_plane *plane,
 {
 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 									  plane);
-	unsigned char i, num_planes;
+
 	struct drm_framebuffer *fb = new_plane_state->fb;
 	struct drm_crtc *crtc = new_plane_state->crtc;
 	struct vs_crtc *vs_crtc = to_vs_crtc(crtc);
 	struct vs_dc *dc = dev_get_drvdata(vs_crtc->dev);
-	struct vs_plane_state *plane_state = to_vs_plane_state(new_plane_state);
 
 	if (!crtc || !fb)
 		return 0;