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perf: riscv: Add SiFive Private L2 cache and PMU driver
The SiFive private L2 cache PMU is supports per-task profiling
and event counting. Users can use the perf tool to profile by
event name and event id.
Example: $ perf stat -e /sifive_u74_l2_pmu/inner_acquire_block_btot/
-e /sifive_u74_l2_pmu/inner_acquire_block_ntob/
-e /sifive_u74_l2_pmu/inner_acquire_block_ntot/ ls
Performance counter stats for 'CPU(s) 0':
300 sifive_u74_l2_pmu/inner_acquire_block_btot/
17801 sifive_u74_l2_pmu/inner_acquire_block_ntob/
5253 sifive_u74_l2_pmu/inner_acquire_block_ntot/
0.088917326 seconds time elapsed
$ perf stat -e /sifive_u74_l2_pmu/event=0x10001/
-e /sifive_u74_l2_pmu/event=0x4001/
-e /sifive_u74_l2_pmu/event=0x8001/ ls
Performance counter stats for 'CPU(s) 0':
251 sifive_u74_l2_pmu/event=0x10001/
2620 sifive_u74_l2_pmu/event=0x4001/
644 sifive_u74_l2_pmu/event=0x8001/
0.092827110 seconds time elapsed
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
This commit is contained in:
Minda Chen
Hal Feng
parent
1d47e4f138
commit
57cfc280b5
5 changed files with 569 additions and 1 deletions
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@ -234,4 +234,14 @@ config CXL_PMU
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If unsure say 'm'.
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config SIFIVE_U74_L2_PMU
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bool "Sifive U74 L2 Cache PMU"
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depends on SIFIVE_CCACHE && PERF_EVENTS
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default y
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help
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Support for the private L2 cache controller performance monitor unit
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(PMU) on SiFive platforms. The SiFive private L2 PMU can monitor the
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each hart L2 cache performance and it consists of a set of event
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programmable counters and their event selector registers.
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endmenu
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@ -26,3 +26,4 @@ obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) += alibaba_uncore_drw_pmu.o
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obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu/
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obj-$(CONFIG_MESON_DDR_PMU) += amlogic/
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obj-$(CONFIG_CXL_PMU) += cxl_pmu.o
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obj-$(CONFIG_SIFIVE_U74_L2_PMU) += sifive_u74_l2_pmu.o
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532
drivers/perf/sifive_u74_l2_pmu.c
Normal file
532
drivers/perf/sifive_u74_l2_pmu.c
Normal file
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@ -0,0 +1,532 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SiFive private L2 cache controller PMU Driver
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*
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* Copyright (C) 2018-2023 SiFive, Inc.
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*/
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#define pr_fmt(fmt) "pL2CACHE_PMU: " fmt
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#include <linux/kprobes.h>
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#include <linux/kernel.h>
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#include <linux/kdebug.h>
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#include <linux/mutex.h>
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#include <linux/bitmap.h>
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#include <linux/perf_event.h>
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#include <linux/atomic.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/cpu_pm.h>
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#define SIFIVE_PL2_PMU_MAX_COUNTERS 64
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#define SIFIVE_PL2_SELECT_BASE_OFFSET 0x2000
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#define SIFIVE_PL2_COUNTER_BASE_OFFSET 0x3000
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#define SIFIVE_PL2_COUNTER_MASK GENMASK_ULL(63, 0)
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struct sifive_u74_l2_pmu_event {
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struct perf_event **events;
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void __iomem *event_counter_base;
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void __iomem *event_select_base;
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u32 counters;
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DECLARE_BITMAP(used_mask, SIFIVE_PL2_PMU_MAX_COUNTERS);
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};
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struct sifive_u74_l2_pmu {
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struct pmu *pmu;
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};
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static bool pl2pmu_init_done;
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static struct sifive_u74_l2_pmu sifive_u74_l2_pmu;
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static DEFINE_PER_CPU(struct sifive_u74_l2_pmu_event, sifive_u74_l2_pmu_event);
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#ifndef readq
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static inline unsigned long long readq(void __iomem *addr)
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{
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return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
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}
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#endif
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#ifndef writeq
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static inline void writeq(unsigned long long v, void __iomem *addr)
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{
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writel(lower_32_bits(v), addr);
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writel(upper_32_bits(v), addr + 4);
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}
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#endif
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/* formats */
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static ssize_t sifive_u74_l2_pmu_format_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct dev_ext_attribute *eattr;
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eattr = container_of(attr, struct dev_ext_attribute, attr);
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return sysfs_emit(buf, "%s\n", (char *)eattr->var);
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}
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#define SIFIVE_PL2_PMU_PMU_FORMAT_ATTR(_name, _config) \
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(&((struct dev_ext_attribute[]) { \
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{ .attr = __ATTR(_name, 0444, sifive_u74_l2_pmu_format_show, NULL),\
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.var = (void *)_config, } \
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})[0].attr.attr)
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static struct attribute *sifive_u74_l2_pmu_formats[] = {
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SIFIVE_PL2_PMU_PMU_FORMAT_ATTR(event, "config:0-63"),
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NULL,
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};
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static struct attribute_group sifive_u74_l2_pmu_format_group = {
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.name = "format",
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.attrs = sifive_u74_l2_pmu_formats,
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};
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/* events */
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static ssize_t sifive_u74_l2_pmu_event_show(struct device *dev,
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struct device_attribute *attr,
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char *page)
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{
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struct perf_pmu_events_attr *pmu_attr;
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pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
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return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
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}
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#define SET_EVENT_SELECT(_event, _set) (((u64)1 << ((_event) + 8)) | (_set))
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#define PL2_PMU_EVENT_ATTR(_name, _event, _set) \
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PMU_EVENT_ATTR_ID(_name, sifive_u74_l2_pmu_event_show, \
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SET_EVENT_SELECT(_event, _set))
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enum pl2_pmu_event_set1 {
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INNER_PUT_FULL_DATA = 0,
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INNER_PUT_PARTIAL_DATA,
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INNER_ARITHMETIC_DATA,
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INNER_GET,
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INNER_PREFETCH_READ,
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INNER_PREFETCH_WRITE,
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INNER_ACQUIRE_BLOCK_NTOB,
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INNER_ACQUIRE_BLOCK_NTOT,
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INNER_ACQUIRE_BLOCK_BTOT,
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INNER_ACQUIRE_PERM_NTOT,
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INNER_ACQUIRE_PERM_BTOT,
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INNER_RELEASE_TTOB,
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INNER_RELEASE_TTON,
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INNER_RELEASE_BTON,
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INNER_RELEASE_DATA_TTOB,
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INNER_RELEASE_DATA_TTON,
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INNER_RELEASE_DATA_BTON,
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OUTER_PROBE_BLOCK_TOT,
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OUTER_PROBE_BLOCK_TOB,
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OUTER_PROBE_BLOCK_TON,
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PL2_PMU_MAX_EVENT1_IDX
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};
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enum pl2_pmu_event_set2 {
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INNER_PUT_FULL_DATA_HIT = 0,
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INNER_PUT_PARTIAL_DATA_HIT,
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INNER_ARITHMETIC_DATA_HIT,
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INNER_GET_HIT,
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INNER_PREFETCH_READ_HIT,
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INNER_ACQUIRE_BLOCK_NTOB_HIT,
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INNER_ACQUIRE_PERM_NTOT_HIT,
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INNER_RELEASE_TTOB_HIT,
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INNER_RELEASE_DATA_TTOB_HIT,
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OUTER_PROBE_BLOCK_TOT_HIT,
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INNER_PUT_FULL_DATA_HIT_SHARED,
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INNER_PUT_PARTIAL_DATA_HIT_SHARED,
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INNER_ARITHMETIC_DATA_HIT_SHARED,
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INNER_GET_HIT_SHARED,
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INNER_PREFETCH_READ_HIT_SHARED,
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INNER_ACQUIRE_BLOCK_HIT_SHARED,
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INNER_ACQUIRE_PERM_NTOT_HIT_SHARED,
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OUTER_PROBE_BLOCK_TOT_HIT_SHARED,
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OUTER_PROBE_BLOCK_TOT_HIT_DIRTY,
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PL2_PMU_MAX_EVENT2_IDX
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};
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enum pl2_pmu_event_set3 {
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OUTER_ACQUIRE_BLOCK_NTOB,
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OUTER_ACQUIRE_BLOCK_NTOT,
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OUTER_ACQUIRE_BLOCK_BTOT,
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OUTER_ACQUIRE_PERM_NTOT,
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OUTER_ACQUIRE_PERM_BTOT,
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OUTER_RELEARE_TTOB,
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OUTER_RELEARE_TTON,
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OUTER_RELEARE_BTON,
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OUTER_RELEARE_DATA_TTOB,
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OUTER_RELEARE_DATA_TTON,
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OUTER_RELEARE_DATA_BTON,
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INNER_PROBE_BLOCK_TOT,
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INNER_PROBE_BLOCK_TOB,
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INNER_PROBE_BLOCK_TON,
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PL2_PMU_MAX_EVENT3_IDX
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};
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enum pl2_pmu_event_set4 {
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INNER_HINT_HITS_MSHR = 0,
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PL2_PMU_MAX_EVENT4_IDX
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};
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static struct attribute *sifive_u74_l2_pmu_events[] = {
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PL2_PMU_EVENT_ATTR(inner_put_full_data, INNER_PUT_FULL_DATA, 1),
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PL2_PMU_EVENT_ATTR(inner_put_partial_data, INNER_PUT_PARTIAL_DATA, 1),
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PL2_PMU_EVENT_ATTR(inner_arithmetic_data, INNER_ARITHMETIC_DATA, 1),
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PL2_PMU_EVENT_ATTR(inner_get, INNER_GET, 1),
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PL2_PMU_EVENT_ATTR(inner_prefetch_read, INNER_PREFETCH_READ, 1),
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PL2_PMU_EVENT_ATTR(inner_prefetch_write, INNER_PREFETCH_WRITE, 1),
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PL2_PMU_EVENT_ATTR(inner_acquire_block_ntob, INNER_ACQUIRE_BLOCK_NTOB, 1),
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PL2_PMU_EVENT_ATTR(inner_acquire_block_ntot, INNER_ACQUIRE_BLOCK_NTOT, 1),
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PL2_PMU_EVENT_ATTR(inner_acquire_block_btot, INNER_ACQUIRE_BLOCK_BTOT, 1),
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PL2_PMU_EVENT_ATTR(inner_acquire_perm_ntot, INNER_ACQUIRE_PERM_NTOT, 1),
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PL2_PMU_EVENT_ATTR(inner_acquire_perm_btot, INNER_ACQUIRE_PERM_BTOT, 1),
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PL2_PMU_EVENT_ATTR(inner_release_ttob, INNER_RELEASE_TTOB, 1),
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PL2_PMU_EVENT_ATTR(inner_release_tton, INNER_RELEASE_TTON, 1),
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PL2_PMU_EVENT_ATTR(inner_release_bton, INNER_RELEASE_BTON, 1),
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PL2_PMU_EVENT_ATTR(inner_release_data_ttob, INNER_RELEASE_DATA_TTOB, 1),
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PL2_PMU_EVENT_ATTR(inner_release_data_tton, INNER_RELEASE_DATA_TTON, 1),
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PL2_PMU_EVENT_ATTR(inner_release_data_bton, INNER_RELEASE_DATA_BTON, 1),
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PL2_PMU_EVENT_ATTR(outer_probe_block_tot, OUTER_PROBE_BLOCK_TOT, 1),
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PL2_PMU_EVENT_ATTR(outer_probe_block_tob, OUTER_PROBE_BLOCK_TOB, 1),
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PL2_PMU_EVENT_ATTR(outer_probe_block_ton, OUTER_PROBE_BLOCK_TON, 1),
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PL2_PMU_EVENT_ATTR(inner_put_full_data_hit, INNER_PUT_FULL_DATA_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_put_partial_data_hit, INNER_PUT_PARTIAL_DATA_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_arithmetic_data_hit, INNER_ARITHMETIC_DATA_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_get_hit, INNER_GET_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_prefetch_read_hit, INNER_PREFETCH_READ_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_acquire_block_ntob_hit, INNER_ACQUIRE_BLOCK_NTOB_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_acquire_perm_ntot_hit, INNER_ACQUIRE_PERM_NTOT_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_release_ttob_hit, INNER_RELEASE_TTOB_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_release_data_ttob_hit, INNER_RELEASE_DATA_TTOB_HIT, 2),
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PL2_PMU_EVENT_ATTR(outer_probe_block_tot_hit, OUTER_PROBE_BLOCK_TOT_HIT, 2),
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PL2_PMU_EVENT_ATTR(inner_put_full_data_hit_shared, INNER_PUT_FULL_DATA_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_put_partial_data_hit_shared, INNER_PUT_PARTIAL_DATA_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_arithmetic_data_hit_shared, INNER_ARITHMETIC_DATA_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_get_hit_shared, INNER_GET_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_prefetch_read_hit_shared, INNER_PREFETCH_READ_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_acquire_block_hit_shared, INNER_ACQUIRE_BLOCK_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(inner_acquire_perm_hit_shared, INNER_ACQUIRE_PERM_NTOT_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(outer_probe_block_tot_hit_shared, OUTER_PROBE_BLOCK_TOT_HIT_SHARED, 2),
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PL2_PMU_EVENT_ATTR(outer_probe_block_tot_hit_dirty, OUTER_PROBE_BLOCK_TOT_HIT_DIRTY, 2),
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PL2_PMU_EVENT_ATTR(outer_acquire_block_ntob, OUTER_ACQUIRE_BLOCK_NTOB, 3),
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PL2_PMU_EVENT_ATTR(outer_acquire_block_ntot, OUTER_ACQUIRE_BLOCK_NTOT, 3),
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PL2_PMU_EVENT_ATTR(outer_acquire_block_btot, OUTER_ACQUIRE_BLOCK_BTOT, 3),
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PL2_PMU_EVENT_ATTR(outer_acquire_perm_ntot, OUTER_ACQUIRE_PERM_NTOT, 3),
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PL2_PMU_EVENT_ATTR(outer_acquire_perm_btot, OUTER_ACQUIRE_PERM_BTOT, 3),
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PL2_PMU_EVENT_ATTR(outer_release_ttob, OUTER_RELEARE_TTOB, 3),
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PL2_PMU_EVENT_ATTR(outer_release_tton, OUTER_RELEARE_TTON, 3),
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PL2_PMU_EVENT_ATTR(outer_release_bton, OUTER_RELEARE_BTON, 3),
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PL2_PMU_EVENT_ATTR(outer_release_data_ttob, OUTER_RELEARE_DATA_TTOB, 3),
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PL2_PMU_EVENT_ATTR(outer_release_data_tton, OUTER_RELEARE_DATA_TTON, 3),
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PL2_PMU_EVENT_ATTR(outer_release_data_bton, OUTER_RELEARE_DATA_BTON, 3),
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PL2_PMU_EVENT_ATTR(inner_probe_block_tot, INNER_PROBE_BLOCK_TOT, 3),
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PL2_PMU_EVENT_ATTR(inner_probe_block_tob, INNER_PROBE_BLOCK_TOB, 3),
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PL2_PMU_EVENT_ATTR(inner_probe_block_ton, INNER_PROBE_BLOCK_TON, 3),
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PL2_PMU_EVENT_ATTR(inner_hint_hits_mshr, INNER_HINT_HITS_MSHR, 4),
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NULL
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};
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static struct attribute_group sifive_u74_l2_pmu_events_group = {
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.name = "events",
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.attrs = sifive_u74_l2_pmu_events,
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};
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/*
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* Per PMU device attribute groups
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*/
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static const struct attribute_group *sifive_u74_l2_pmu_attr_grps[] = {
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&sifive_u74_l2_pmu_format_group,
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&sifive_u74_l2_pmu_events_group,
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NULL,
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};
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/*
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* Low-level functions: reading and writing counters
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*/
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static inline u64 read_counter(int idx)
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{
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struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
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if (WARN_ON_ONCE(idx < 0 || idx > ptr->counters))
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return -EINVAL;
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return readq(ptr->event_counter_base + idx * 8);
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}
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static inline void write_counter(int idx, u64 val)
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{
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struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
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writeq(val, ptr->event_counter_base + idx * 8);
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}
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/*
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* pmu->read: read and update the counter
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*/
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static void sifive_u74_l2_pmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 prev_raw_count, new_raw_count;
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u64 oldval;
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int idx = hwc->idx;
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u64 delta;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = read_counter(idx);
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oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count);
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} while (oldval != prev_raw_count);
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/* delta is the value to update the counter we maintain in the kernel. */
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delta = (new_raw_count - prev_raw_count) & SIFIVE_PL2_COUNTER_MASK;
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local64_add(delta, &event->count);
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}
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/*
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* State transition functions:
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*
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* stop()/start() & add()/del()
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*/
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/*
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* pmu->stop: stop the counter
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*/
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static void sifive_u74_l2_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
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/* Disable this counter to count events */
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writeq(0, ptr->event_select_base + (hwc->idx * 8));
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
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sifive_u74_l2_pmu_read(event);
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hwc->state |= PERF_HES_UPTODATE;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu->start: start the event.
|
||||
*/
|
||||
static void sifive_u74_l2_pmu_start(struct perf_event *event, int flags)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
|
||||
|
||||
if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
|
||||
return;
|
||||
|
||||
if (flags & PERF_EF_RELOAD)
|
||||
WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
|
||||
|
||||
hwc->state = 0;
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
/* Set initial value 0 */
|
||||
local64_set(&hwc->prev_count, 0);
|
||||
write_counter(hwc->idx, 0);
|
||||
|
||||
/* Enable counter to count these events */
|
||||
writeq(hwc->config, ptr->event_select_base + (hwc->idx * 8));
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu->add: add the event to PMU.
|
||||
*/
|
||||
static int sifive_u74_l2_pmu_add(struct perf_event *event, int flags)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
|
||||
int idx;
|
||||
u64 config = event->attr.config;
|
||||
u64 set = config & 0xff;
|
||||
u64 ev_type = config >> 8;
|
||||
|
||||
/* Check if this is a valid set and event. */
|
||||
switch (set) {
|
||||
case 1:
|
||||
if (ev_type >= (BIT_ULL(PL2_PMU_MAX_EVENT1_IDX)))
|
||||
return -ENOENT;
|
||||
break;
|
||||
case 2:
|
||||
if (ev_type >= (BIT_ULL(PL2_PMU_MAX_EVENT2_IDX)))
|
||||
return -ENOENT;
|
||||
break;
|
||||
case 3:
|
||||
if (ev_type >= (BIT_ULL(PL2_PMU_MAX_EVENT3_IDX)))
|
||||
return -ENOENT;
|
||||
break;
|
||||
case 4:
|
||||
if (ev_type >= (BIT_ULL(PL2_PMU_MAX_EVENT4_IDX)))
|
||||
return -ENOENT;
|
||||
break;
|
||||
case 0:
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
idx = find_first_zero_bit(ptr->used_mask, ptr->counters);
|
||||
/* The counters are all in use. */
|
||||
if (idx == ptr->counters)
|
||||
return -EAGAIN;
|
||||
|
||||
set_bit(idx, ptr->used_mask);
|
||||
|
||||
/* Found an available counter idx for this event. */
|
||||
hwc->idx = idx;
|
||||
ptr->events[hwc->idx] = event;
|
||||
|
||||
hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
|
||||
|
||||
if (flags & PERF_EF_START)
|
||||
sifive_u74_l2_pmu_start(event, PERF_EF_RELOAD);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* pmu->del: delete the event from PMU.
|
||||
*/
|
||||
static void sifive_u74_l2_pmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
/* Stop the counter and release this counter. */
|
||||
ptr->events[hwc->idx] = NULL;
|
||||
sifive_u74_l2_pmu_stop(event, PERF_EF_UPDATE);
|
||||
clear_bit(hwc->idx, ptr->used_mask);
|
||||
perf_event_update_userpage(event);
|
||||
}
|
||||
|
||||
/*
|
||||
* Event Initialization/Finalization
|
||||
*/
|
||||
|
||||
static int sifive_u74_l2_pmu_event_init(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
/* Don't allocate hw counter yet. */
|
||||
hwc->idx = -1;
|
||||
hwc->config = event->attr.config;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialization
|
||||
*/
|
||||
|
||||
static struct pmu sifive_u74_l2_generic_pmu = {
|
||||
.name = "sifive_u74_l2_pmu",
|
||||
.task_ctx_nr = perf_sw_context,
|
||||
.event_init = sifive_u74_l2_pmu_event_init,
|
||||
.add = sifive_u74_l2_pmu_add,
|
||||
.del = sifive_u74_l2_pmu_del,
|
||||
.start = sifive_u74_l2_pmu_start,
|
||||
.stop = sifive_u74_l2_pmu_stop,
|
||||
.read = sifive_u74_l2_pmu_read,
|
||||
.attr_groups = sifive_u74_l2_pmu_attr_grps,
|
||||
.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT,
|
||||
};
|
||||
|
||||
static struct sifive_u74_l2_pmu sifive_u74_l2_pmu = {
|
||||
.pmu = &sifive_u74_l2_generic_pmu,
|
||||
};
|
||||
|
||||
/*
|
||||
* PM notifer for suspend to ram
|
||||
*/
|
||||
#ifdef CONFIG_CPU_PM
|
||||
static int sifive_u74_l2_pmu_pm_notify(struct notifier_block *b, unsigned long cmd,
|
||||
void *v)
|
||||
{
|
||||
struct sifive_u74_l2_pmu_event *ptr = this_cpu_ptr(&sifive_u74_l2_pmu_event);
|
||||
struct perf_event *event;
|
||||
int idx;
|
||||
int enabled_event = bitmap_weight(ptr->used_mask, ptr->counters);
|
||||
|
||||
if (!enabled_event)
|
||||
return NOTIFY_OK;
|
||||
|
||||
for (idx = 0; idx < ptr->counters; idx++) {
|
||||
event = ptr->events[idx];
|
||||
if (!event)
|
||||
continue;
|
||||
|
||||
switch (cmd) {
|
||||
case CPU_PM_ENTER:
|
||||
/* Stop and update the counter */
|
||||
sifive_u74_l2_pmu_stop(event, PERF_EF_UPDATE);
|
||||
break;
|
||||
case CPU_PM_ENTER_FAILED:
|
||||
case CPU_PM_EXIT:
|
||||
/* Restore and enable the counter */
|
||||
sifive_u74_l2_pmu_start(event, PERF_EF_RELOAD);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block sifive_u74_l2_pmu_pm_notifier_block = {
|
||||
.notifier_call = sifive_u74_l2_pmu_pm_notify,
|
||||
};
|
||||
|
||||
static inline void sifive_u74_l2_pmu_pm_init(void)
|
||||
{
|
||||
cpu_pm_register_notifier(&sifive_u74_l2_pmu_pm_notifier_block);
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void sifive_u74_l2_pmu_pm_init(void) { }
|
||||
#endif /* CONFIG_CPU_PM */
|
||||
|
||||
int sifive_u74_l2_pmu_probe(struct device_node *pl2_node,
|
||||
void __iomem *pl2_base, int cpu)
|
||||
{
|
||||
struct sifive_u74_l2_pmu_event *ptr = per_cpu_ptr(&sifive_u74_l2_pmu_event, cpu);
|
||||
int ret;
|
||||
|
||||
/* Get counter numbers. */
|
||||
ptr->counters = SIFIVE_PL2_PMU_MAX_COUNTERS;
|
||||
pr_info("perfmon-counters: 64 for CPU %d\n", cpu);
|
||||
|
||||
/* Allocate perf_event. */
|
||||
ptr->events = kcalloc(ptr->counters, sizeof(struct perf_event), GFP_KERNEL);
|
||||
if (!ptr->events)
|
||||
return -ENOMEM;
|
||||
|
||||
ptr->event_select_base = pl2_base + SIFIVE_PL2_SELECT_BASE_OFFSET;
|
||||
ptr->event_counter_base = pl2_base + SIFIVE_PL2_COUNTER_BASE_OFFSET;
|
||||
|
||||
if (!pl2pmu_init_done) {
|
||||
ret = perf_pmu_register(sifive_u74_l2_pmu.pmu, sifive_u74_l2_pmu.pmu->name, -1);
|
||||
if (ret) {
|
||||
pr_err("Failed to register sifive_u74_l2_pmu.pmu: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
sifive_u74_l2_pmu_pm_init();
|
||||
pl2pmu_init_done = true;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(sifive_u74_l2_pmu_probe);
|
||||
|
|
@ -18,6 +18,7 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/cacheinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include "sifive_pl2.h"
|
||||
#include <soc/sifive/sifive_ccache.h>
|
||||
|
||||
#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
|
||||
|
|
@ -263,7 +264,7 @@ static int __init sifive_ccache_init(void)
|
|||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
int i, rc, intr_num;
|
||||
int i, rc, intr_num, cpu;
|
||||
u64 __maybe_unused offset;
|
||||
|
||||
np = of_find_matching_node(NULL, sifive_ccache_ids);
|
||||
|
|
@ -315,6 +316,16 @@ static int __init sifive_ccache_init(void)
|
|||
|
||||
ccache_config_read();
|
||||
|
||||
if (IS_ENABLED(CONFIG_SIFIVE_U74_L2_PMU)) {
|
||||
for_each_cpu(cpu, cpu_possible_mask) {
|
||||
rc = sifive_u74_l2_pmu_probe(np, ccache_base, cpu);
|
||||
if (rc) {
|
||||
pr_err("Failed to probe sifive_u74_l2_pmu driver.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ccache_cache_ops.get_priv_group = ccache_get_priv_group;
|
||||
riscv_set_cacheinfo_ops(&ccache_cache_ops);
|
||||
|
||||
|
|
|
|||
14
drivers/soc/sifive/sifive_pl2.h
Normal file
14
drivers/soc/sifive/sifive_pl2.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2023 SiFive, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SIFIVE_PL2_H
|
||||
#define _SIFIVE_PL2_H
|
||||
|
||||
#define SIFIVE_PL2_PMCLIENT_OFFSET 0x2800
|
||||
|
||||
int sifive_u74_l2_pmu_probe(struct device_node *pl2_node,
|
||||
void __iomem *pl2_base, int cpu);
|
||||
#endif /*_SIFIVE_PL2_H */
|
||||
Loading…
Add table
Reference in a new issue