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riscv: dts: Add JH7100 and BeagleV Starlight support

Browse source 
Based on the device tree in https://github.com/starfive-tech/u-boot/
with contributions from:
yanhong.wang <yanhong.wang@starfivetech.com>
Huan.Feng <huan.feng@starfivetech.com>
ke.zhu <ke.zhu@starfivetech.com>
yiming.li <yiming.li@starfivetech.com>
jack.zhu <jack.zhu@starfivetech.com>
Samin Guo <samin.guo@starfivetech.com>
Chenjieqin <Jessica.Chen@starfivetech.com>
bo.li <bo.li@starfivetech.com>

Rearranged, cleanups, fixes, TPS65086 and pins added by Emil.
Cleanups, fixes, LED and clocks added by Geert.
Cleanups and GPIO fixes from Drew.
Thermal zone added by Stephen.
PWM pins added by Jianlong.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
This commit is contained in:
TekkamanV 2021-01-23 02:52:17 +08:00 • committed by Emil Renner Berthing
parent 6ee7a7055a
commit 59af5e130d
4 changed files with 1401 additions and 1 deletions
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2
arch/riscv/boot/dts/Makefile
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@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += sifive starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip

2
arch/riscv/boot/dts/starfive/Makefile Normal file
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@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_STARFIVE_VIC7100) += jh7100-beaglev-starlight.dtb

774
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts Normal file
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@ -0,0 +1,774 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/dts-v1/;
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/starfive_fb.h>
/ {
model = "BeagleV Starlight Beta";
compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100";
aliases {
mshc0 = &sdio0;
mshc1 = &sdio1;
serial0 = &uart3;
serial1 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <6250000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x2 0x0>;
};
leds {
compatible = "gpio-leds";
led-ack {
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
linux,default-trigger = "heartbeat";
label = "ack";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x28000000>;
alignment = <0x0 0x1000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
linux,cma-default;
};
jpu_reserved: framebuffer@c9000000 {
reg = <0x0 0xc9000000 0x0 0x4000000>;
};
nvdla_reserved: framebuffer@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0x28000000>;
};
vin_reserved: framebuffer@f9000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xf9000000 0x0 0x1000000>;
};
sffb_reserved: framebuffer@fb000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0xfb000000 0x0 0x2000000>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
};
};
&gmac {
snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins>;
};
&gpio {
/* don't reset gpio mux for serial console on uart3 */
starfive,keep-gpiomux = <13 14>;
gmac_pins: gmac-0 {
gtxclk-pins {
pins = <PAD_FUNC_SHARE(115)>;
bias-pull-up;
drive-strength = <35>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
miitxclk-pins {
pins = <PAD_FUNC_SHARE(116)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
tx-pins {
pins = <PAD_FUNC_SHARE(117)>,
<PAD_FUNC_SHARE(119)>,
<PAD_FUNC_SHARE(120)>,
<PAD_FUNC_SHARE(121)>,
<PAD_FUNC_SHARE(122)>,
<PAD_FUNC_SHARE(123)>,
<PAD_FUNC_SHARE(124)>,
<PAD_FUNC_SHARE(125)>,
<PAD_FUNC_SHARE(126)>;
bias-pull-up;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rxclk-pins {
pins = <PAD_FUNC_SHARE(127)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <6>;
};
rxer-pins {
pins = <PAD_FUNC_SHARE(129)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pins = <PAD_FUNC_SHARE(128)>,
<PAD_FUNC_SHARE(130)>,
<PAD_FUNC_SHARE(131)>,
<PAD_FUNC_SHARE(132)>,
<PAD_FUNC_SHARE(133)>,
<PAD_FUNC_SHARE(134)>,
<PAD_FUNC_SHARE(135)>,
<PAD_FUNC_SHARE(136)>,
<PAD_FUNC_SHARE(137)>,
<PAD_FUNC_SHARE(138)>,
<PAD_FUNC_SHARE(139)>,
<PAD_FUNC_SHARE(140)>,
<PAD_FUNC_SHARE(141)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(62, GPO_LOW,
GPO_I2C0_PAD_SCK_OEN,
GPI_I2C0_PAD_SCK_IN)>,
<GPIOMUX(61, GPO_LOW,
GPO_I2C0_PAD_SDA_OEN,
GPI_I2C0_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
i2c1_pins: i2c1-0 {
i2c-pins {
pinmux = <GPIOMUX(47, GPO_LOW,
GPO_I2C1_PAD_SCK_OEN,
GPI_I2C1_PAD_SCK_IN)>,
<GPIOMUX(48, GPO_LOW,
GPO_I2C1_PAD_SDA_OEN,
GPI_I2C1_PAD_SDA_IN)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
i2c2_pins: i2c2-0 {
i2c-pins {
pinmux = <GPIOMUX(60, GPO_LOW,
GPO_I2C2_PAD_SCK_OEN,
GPI_I2C2_PAD_SCK_IN)>,
<GPIOMUX(59, GPO_LOW,
GPO_I2C2_PAD_SDA_OEN,
GPI_I2C2_PAD_SDA_IN)>;
bias-disable; /* external pull-up */
input-enable;
input-schmitt-enable;
};
};
pwm_pins: pwm-0 {
pwm-pins {
pinmux = <GPIOMUX(7,
GPO_PWM_PAD_OUT_BIT0,
GPO_PWM_PAD_OE_N_BIT0,
GPI_NONE)>,
<GPIOMUX(5,
GPO_PWM_PAD_OUT_BIT1,
GPO_PWM_PAD_OE_N_BIT1,
GPI_NONE)>,
<GPIOMUX(45,
GPO_PWM_PAD_OUT_BIT2,
GPO_PWM_PAD_OE_N_BIT2,
GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
sdio0_pins: sdio0-0 {
clk-pins {
pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
GPI_SDIO0_PAD_CARD_DETECT_N)>,
<GPIOMUX(53,
GPO_SDIO0_PAD_CCMD_OUT,
GPO_SDIO0_PAD_CCMD_OEN,
GPI_SDIO0_PAD_CCMD_IN)>,
<GPIOMUX(49,
GPO_SDIO0_PAD_CDATA_OUT_BIT0,
GPO_SDIO0_PAD_CDATA_OEN_BIT0,
GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(50,
GPO_SDIO0_PAD_CDATA_OUT_BIT1,
GPO_SDIO0_PAD_CDATA_OEN_BIT1,
GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(51,
GPO_SDIO0_PAD_CDATA_OUT_BIT2,
GPO_SDIO0_PAD_CDATA_OEN_BIT2,
GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(52,
GPO_SDIO0_PAD_CDATA_OUT_BIT3,
GPO_SDIO0_PAD_CDATA_OEN_BIT3,
GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
sdio1_pins: sdio1-0 {
clk-pins {
pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
sdio-pins {
pinmux = <GPIOMUX(29,
GPO_SDIO1_PAD_CCMD_OUT,
GPO_SDIO1_PAD_CCMD_OEN,
GPI_SDIO1_PAD_CCMD_IN)>,
<GPIOMUX(36,
GPO_SDIO1_PAD_CDATA_OUT_BIT0,
GPO_SDIO1_PAD_CDATA_OEN_BIT0,
GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
<GPIOMUX(30,
GPO_SDIO1_PAD_CDATA_OUT_BIT1,
GPO_SDIO1_PAD_CDATA_OEN_BIT1,
GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
<GPIOMUX(34,
GPO_SDIO1_PAD_CDATA_OUT_BIT2,
GPO_SDIO1_PAD_CDATA_OEN_BIT2,
GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
<GPIOMUX(31,
GPO_SDIO1_PAD_CDATA_OUT_BIT3,
GPO_SDIO1_PAD_CDATA_OEN_BIT3,
GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
};
spi2_pins: spi2-0 {
mosi-pin {
pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
miso-pin {
pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
GPI_SPI2_PAD_RXD)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
sck-pin {
pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
ss-pins {
pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
GPO_ENABLE, GPI_NONE)>,
<GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
uart0_pins: uart0-0 {
rx-pins {
pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
GPI_UART0_PAD_SIN)>,
<GPIOMUX(39, GPO_LOW, GPO_DISABLE,
GPI_UART0_PAD_CTSN)>;
bias-pull-up;
input-enable;
input-schmitt-enable;
};
tx-pins {
pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
GPO_ENABLE, GPI_NONE)>,
<GPIOMUX(42, GPO_UART0_PAD_RTSN,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
input-disable;
input-schmitt-disable;
};
};
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
GPI_UART3_PAD_SIN)>;
bias-pull-up;
drive-strength = <14>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
tx-pins {
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
GPO_ENABLE, GPI_NONE)>;
bias-disable;
drive-strength = <35>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&i2c0 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
imx219@10 {
compatible = "imx219";
reg = <0x10>;
reset-gpio = <&gpio 58 GPIO_ACTIVE_HIGH>;
};
pmic@5e {
compatible = "ti,tps65086";
reg = <0x5e>;
gpio-controller;
#gpio-cells = <2>;
regulators {
};
};
tda998x@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
};
};
&i2c1 {
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <100>;
i2c-scl-falling-time-ns = <100>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
i2c-sda-hold-time-ns = <300>;
i2c-sda-falling-time-ns = <500>;
i2c-scl-falling-time-ns = <500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
seeed_plane_i2c@45 {
compatible = "seeed_panel";
reg = <0x45>;
};
};
&osc_sys {
clock-frequency = <25000000>;
};
&osc_aud {
clock-frequency = <27000000>;
};
&ptc {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&qspi {
nor_flash: nor-flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <31250000>;
page-size = <256>;
block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
nand_flash: nand-flash@1 {
compatible = "spi-flash-nand";
reg = <1>;
spi-max-frequency = <31250000>;
page-size = <2048>;
block-size = <17>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <1>;
cdns,tsd2d-ns = <1>;
cdns,tchsh-ns = <1>;
cdns,tslch-ns = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&sdio0 {
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_pins>;
status = "okay";
};
&sdio1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
cap-power-off-card;
max-frequency = <10000000>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_pins>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&sfivefb {
status = "okay";
/*
pp1 {
pp-id = <1>;
fifo-out;
src-format = <COLOR_YUV420_NV21>;
src-width = <800>;
src-height = <480>;
dst-format = <COLOR_RGB888_ARGB>;
dst-width = <800>;
dst-height = <480>;
};
*/
tda_998x_1080p {
compatible = "starfive,display-dev";
panel_name = "tda_998x_1080p";
panel_lcd_id = <22>; /* 1080p */
interface_info = "rgb_interface";
refresh_en = <1>;
bits-per-pixel = <16>;
physical-width = <62>;
physical-height = <114>;
panel-width = <1920>;
panel-height = <1080>;
pixel-clock = <78000000>;
/*dyn_fps;*/ /*dynamic frame rate support*/
/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
/*gamma-command-monolithic;*/
/*ce-command-monolithic;*/
/*resume-with-gamma;*/
/*resume-with-ce;*/
/*mipi info*/
mipi-byte-clock = <78000>;
mipi-escape-clock = <13000>;
lane-no = <4>;
display_mode = "video_mode"; /*video_mode, command_mode*/
/*
auto_stop_clklane_en;
im_pin_val;*/
color_bits = <COLOR_CODE_24BIT>;
/*is_18bit_loosely;*/
/*video mode info*/
h-pulse-width = <44>;
h-back-porch = <148>;
h-front-porch = <88>;
v-pulse-width = <5>;
v-back-porch = <36>;
v-front-porch = <4>;
status = "okay";
sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
lp_cmd_en;
/*lp_hfp_en;*/
/*lp_hbp_en;*/
/*lp_vact_en;*/
lp_vfp_en;
lp_vbp_en;
lp_vsa_en;
traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
/*phy info*/
data_tprepare = /bits/ 8 <0>;
data_hs_zero = /bits/ 8 <0>;
data_hs_exit = /bits/ 8 <0>;
data_hs_trail = /bits/ 8 <0>;
/*te info*/
te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
te_enable = <0>;
cm_te_effect_sync_enable = <0>; /*used in command mode*/
te_count_per_sec = <64>; /*used in esd*/
/*ext info*/
/*
crc_rx_en;
ecc_rx_en;
eotp_rx_en;
*/
eotp_tx_en;
dev_read_time = <0x7fff>;
/*type cmd return_count return_code*/
/*id_read_cmd_info = [];*/
/*pre_id_cmd = [];*/
/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
/*pre_esd_cmd = [];*/
/*panel-on-command = [];*/
/*panel-off-command = [];*/
/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
/*
panel-gamma-warm-command = [
];
panel-gamma-nature-command = [
];
panel-gamma-cool-command = [
];
panel-ce-std-command = [
];
panel-ce-vivid-command = [
];
*/
};
seeed_5_inch {
compatible = "starfive,display-dev";
panel_name = "seeed_5_inch";
panel_lcd_id = <22>; /* 480p */
interface_info = "mipi_interface";
refresh_en = <1>;
bits-per-pixel = <24>;
physical-width = <62>;
physical-height = <114>;
panel-width = <800>;
panel-height = <480>;
pixel-clock = <27500000>;
/*dyn_fps;*/ /*dynamic frame rate support*/
fps = <50>;
/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
/*gamma-command-monolithic;*/
/*ce-command-monolithic;*/
/*resume-with-gamma;*/
/*resume-with-ce;*/
/*mipi info*/
mipi-byte-clock = <78000>;
mipi-escape-clock = <13000>;
lane-no = <1>;
display_mode = "video_mode"; /*video_mode, command_mode*/
/*
auto_stop_clklane_en;
im_pin_val;
*/
color_bits = <COLOR_CODE_24BIT>;
/*is_18bit_loosely;*/
/*video mode info*/
h-pulse-width = <10>;
h-back-porch = <20>;
h-front-porch = <50>;
v-pulse-width = <5>;
v-back-porch = <5>;
v-front-porch = <135>;
/*seeed panel mode info*/
dphy_bps = <700000000>;
dsi_burst_mode = <0>;
dsi_sync_pulse = <1>;
// bytes
dsi_hsa = <30>;
dsi_hbp = <211>;
dsi_hfp = <159>;
// lines
dsi_vsa = <5>;
dsi_vbp = <5>;
dsi_vfp = <134>;
status = "okay";
sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
lp_cmd_en;
/*lp_hfp_en;*/
/*lp_hbp_en;*/
/*lp_vact_en;*/
lp_vfp_en;
lp_vbp_en;
lp_vsa_en;
traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
/*phy info*/
data_tprepare = /bits/ 8 <0>;
data_hs_zero = /bits/ 8 <0>;
data_hs_exit = /bits/ 8 <0>;
data_hs_trail = /bits/ 8 <0>;
/*te info*/
te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
te_enable = <0>;
cm_te_effect_sync_enable = <0>; /*used in command mode*/
te_count_per_sec = <64>; /*used in esd*/
/*ext info*/
/*
crc_rx_en;
ecc_rx_en;
eotp_rx_en;
*/
eotp_tx_en;
dev_read_time = <0x7fff>;
/*type cmd return_count return_code*/
/*id_read_cmd_info = [];*/
/*pre_id_cmd = [];*/
/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
/*pre_esd_cmd = [];*/
/*panel-on-command = [];*/
/*panel-off-command = [];*/
/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
/*
panel-gamma-warm-command = [
];
panel-gamma-nature-command = [
];
panel-gamma-cool-command = [
];
panel-ce-std-command = [
];
panel-ce-vivid-command = [
];
*/
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
status = "okay";
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <10000000>;
reg = <0>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "okay";
};
&usb3 {
dr_mode = "host";
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/dts-v1/;
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/starfive_fb.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "starfive,jh7100";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "sifive,u74-mc", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <0>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim0>;
status = "okay";
tlb-split;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
compatible = "sifive,u74-mc", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
reg = <1>;
riscv,isa = "rv64imafdc";
starfive,itim = <&itim1>;
status = "okay";
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
osc_sys: osc_sys {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
osc_aud: osc_aud {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ccache: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <2048>;
cache-size = <2097152>;
cache-unified;
compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
interrupts = <128 131 129 130>;
/*next-level-cache = <&L40 &L36>;*/
reg = <0x0 0x2010000 0x0 0x1000>,
<0x0 0x8000000 0x0 0x2000000>;
reg-names = "control", "sideband";
};
dtim: dtim@1000000 {
compatible = "starfive,dtim0";
reg = <0x0 0x1000000 0x0 0x2000>;
reg-names = "mem";
};
itim0: itim@1808000 {
compatible = "starfive,itim0";
reg = <0x0 0x1808000 0x0 0x8000>;
reg-names = "mem";
};
itim1: itim@1820000 {
compatible = "starfive,itim0";
reg = <0x0 0x1820000 0x0 0x8000>;
reg-names = "mem";
};
clint: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
interrupts-extended = <&cpu0_intc 3>,
<&cpu0_intc 7>,
<&cpu1_intc 3>,
<&cpu1_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu0_intc 9>,
<&cpu1_intc 11>,
<&cpu1_intc 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <127>;
};
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
clocks = <&osc_sys>, <&osc_aud>;
clock-names = "osc_sys", "osc_aud";
#clock-cells = <1>;
};
uart0: serial@11870000 {
compatible = "snps,dw-apb-uart";
interrupts = <92>;
reg = <0x0 0x11870000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&clkgen JH7100_CLK_UART0_CORE>,
<&clkgen JH7100_CLK_UART0_APB>;
clock-names = "baudclk", "apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "disabled";
};
uart1: serial@11880000 {
compatible = "snps,dw-apb-uart";
interrupts = <93>;
reg = <0x0 0x11880000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&clkgen JH7100_CLK_UART1_CORE>,
<&clkgen JH7100_CLK_UART1_APB>;
clock-names = "baudclk", "apb_pclk";
current-clock = <74250000>;
current-speed = <115200>;
status = "disabled";
};
uart2: serial@12430000 {
compatible = "snps,dw-apb-uart";
interrupts = <72>;
reg = <0x0 0x12430000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&clkgen JH7100_CLK_UART2_CORE>,
<&clkgen JH7100_CLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "disabled";
};
uart3: serial@12440000 {
compatible = "snps,dw-apb-uart";
interrupts = <73>;
reg = <0x0 0x12440000 0x0 0x10000>;
reg-io-width = <4>;
reg-shift = <2>;
clocks = <&clkgen JH7100_CLK_UART3_CORE>,
<&clkgen JH7100_CLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
current-clock = <100000000>;
current-speed = <115200>;
status = "disabled";
};
dma2p: dma-controller@100b0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x100b0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
<&clkgen JH7100_CLK_SGDMA2P_AHB>;
clock-names = "core-clk", "cfgr-clk";
interrupts = <2>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <4>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <128>;
status = "okay";
};
dma1p: dma-controller@10500000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x0 0x10500000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
<&clkgen JH7100_CLK_SGDMA1P_BUS>;
clock-names = "core-clk", "cfgr-clk";
interrupts = <1>;
#dma-cells = <1>;
dma-channels = <16>;
snps,dma-masters = <1>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
snps,axi-max-burst-len = <64>;
status = "okay";
};
usb3: usb@104c0000 {
compatible = "cdns,usb3";
reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
<0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
<0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
reg-names = "otg", "xhci", "dev";
interrupts = <44>, <52>, <43>;
interrupt-names = "host", "peripheral", "otg";
phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
maximum-speed = "super-speed";
status = "disabled";
};
gpio: pinctrl@11910000 {
compatible = "starfive,jh7100-pinctrl";
reg = <0x0 0x11910000 0x0 0x10000>,
<0x0 0x11858000 0x0 0x1000>;
reg-names = "gpio", "padctl";
clocks = <&clkgen JH7100_CLK_GPIO_APB>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <32>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0: i2c@118b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
interrupts = <96>;
clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
<&clkgen JH7100_CLK_I2C0_APB>;
clock-names = "ref", "pclk";
status = "disabled";
};
i2c1: i2c@118c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x118c0000 0x0 0x10000>;
interrupts = <97>;
clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
<&clkgen JH7100_CLK_I2C1_APB>;
clock-names = "ref", "pclk";
status = "disabled";
};
i2c2: i2c@12450000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x12450000 0x0 0x10000>;
interrupts = <74>;
clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
<&clkgen JH7100_CLK_I2C2_APB>;
clock-names = "ref", "pclk";
status = "disabled";
};
i2c3: i2c@12460000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x12460000 0x0 0x10000>;
interrupts = <75>;
clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
<&clkgen JH7100_CLK_I2C3_APB>;
clock-names = "ref", "pclk";
status = "disabled";
};
trng: trng@118d0000 {
compatible = "starfive,vic-rng";
reg = <0x0 0x118d0000 0x0 0x10000>;
interrupts = <98>;
clocks = <&clkgen JH7100_CLK_TRNG_APB>;
};
crypto: crypto@100d0000 {
compatible = "starfive,vic-sec";
reg = <0x0 0x100d0000 0x0 0x20000>,
<0x0 0x11800234 0x0 0xc>;
reg-names = "secmem", "secclk";
interrupts = <31>;
clocks = <&clkgen JH7100_CLK_SEC_AHB>;
};
/* gmac device configuration */
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <256 128 64 32 0 0 0>;
};
gmac: ethernet@10020000 {
compatible = "snps,dwmac";
reg = <0x0 0x10020000 0x0 0x10000>;
interrupts = <6 7>;
interrupt-names = "macirq", "eth_wake_irq";
max-frame-size = <9000>;
phy-mode = "rgmii-txid";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <32768>;
tx-fifo-depth = <16384>;
clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
<&clkgen JH7100_CLK_GMAC_AHB>,
<&clkgen JH7100_CLK_GMAC_PTP_REF>;
clock-names = "stmmaceth", "pclk", "ptp_ref";
snps,fixed-burst;
snps,no-pbl-x8 = <1>;
/*snps,force_sf_dma_mode;*/
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
};
nvdla@11940000 {
compatible = "nvidia,nvdla_os_initial";
interrupts = <22>;
memory-region = <&nvdla_reserved>;
reg = <0x0 0x11940000 0x0 0x40000>;
status = "okay";
};
jpu: coadj12@11900000 {
compatible = "cm,codaj12-jpu-1";
reg = <0x0 0x11900000 0x0 0x300>;
memory-region = <&jpu_reserved>;
interrupts = <24>;
clocks = <&clkgen JH7100_CLK_JPEG_APB>;
clock-names = "jpege";
reg-names = "control";
status = "okay";
};
vpu_dec: vpu_dec@118f0000 {
compatible = "c&m,cm511-vpu";
reg = <0 0x118f0000 0 0x10000>;
//memory-region = <&vpu_reserved>;
interrupts = <23>;
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
clock-names = "vcodec";
status = "okay";
};
vpu_enc: vpu_enc@118e0000 {
compatible = "cm,cm521-vpu";
reg = <0x0 0x118e0000 0x0 0x4000>;
interrupts = <26>;
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
clock-names = "vcodec";
reg-names = "control";
};
ptc: pwm@12490000 {
compatible = "starfive,pwm0";
reg = <0x0 0x12490000 0x0 0x10000>;
reg-names = "control";
sifive,approx-period = <100000000>;
clocks = <&clkgen JH7100_CLK_PWM_APB>;
#pwm-cells = <3>;
sifive,npwm = <8>;
status = "disabled";
};
qspi: spi@11860000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x11860000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x20000000>;
interrupts = <3>;
clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
status = "disabled";
spi-max-frequency = <250000000>;
};
spi0: spi@11890000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <94>;
reg = <0x0 0x11890000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
<&clkgen JH7100_CLK_SPI0_APB>;
clock-names = "ssi_clk", "pclk";
status = "disabled";
};
spi1: spi@118a0000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <95>;
reg = <0x0 0x118a0000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
<&clkgen JH7100_CLK_SPI1_APB>;
clock-names = "ssi_clk", "pclk";
status = "disabled";
};
spi2: spi@12410000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
reg = <0x0 0x12410000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
<&clkgen JH7100_CLK_SPI2_APB>;
clock-names = "ssi_clk", "pclk";
status = "disabled";
};
spi3: spi@12420000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
reg = <0x0 0x12420000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
<&clkgen JH7100_CLK_SPI3_APB>;
clock-names = "ssi_clk", "pclk";
status = "disabled";
};
xrp@f0000000 {
compatible = "cdns,xrp";
reg = <0x0 0xf0000000 0x0 0x01ffffff>,
<0x10 0x72000000 0x0 0x00001000>,
<0x10 0x72001000 0x0 0x00fff000>,
<0x0 0x124b0000 0x0 0x00010000>;
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
firmware-name = "vp6_elf";
dsp-irq = <19 20>;
dsp-irq-src = <0x20 0x21>;
intc-irq-mode = <1>;
intc-irq = <0 1>;
interrupts = <27 28>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x0 0x40000000 0x01000000>,
<0xb0000000 0x10 0x70000000 0x3000000>;
dsp@0 {
};
};
sdio0: mmc@10000000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10000000 0x0 0x10000>;
interrupts = <4>;
clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
<&clkgen JH7100_CLK_SDIO0_CCLKINT>;
clock-names = "biu", "ciu";
clock-frequency = <100000000>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
sdio1: mmc@10010000 {
compatible = "snps,dw-mshc";
reg = <0x0 0x10010000 0x0 0x10000>;
interrupts = <5>;
clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
<&clkgen JH7100_CLK_SDIO1_CCLKINT>;
clock-names = "biu", "ciu";
clock-frequency = <100000000>;
data-addr = <0>;
fifo-depth = <32>;
fifo-watermark-aligned;
status = "disabled";
};
sfivefb: sfivefb@12000000 {
compatible = "starfive,vpp-lcdc";
interrupts = <101>, <103>;
interrupt-names = "lcdc_irq", "vpp1_irq";
reg = <0x0 0x12000000 0x0 0x10000>,
<0x0 0x12100000 0x0 0x10000>,
<0x0 0x12040000 0x0 0x10000>,
<0x0 0x12080000 0x0 0x10000>,
<0x0 0x120c0000 0x0 0x10000>,
<0x0 0x12240000 0x0 0x10000>,
<0x0 0x12250000 0x0 0x10000>,
<0x0 0x12260000 0x0 0x10000>;
reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
memory-region = <&sffb_reserved>;
#if 0 // FIXME uart clocks can't be right for lcdc
clocks = <&clkgen JH7100_CLK_UART>,
<&clkgen JH7100_CLK_APB2>;
#endif
clock-names = "baudclk", "apb_pclk";
ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
status = "disabled";
};
vin_sysctl: vin_sysctl@19800000 {
compatible = "starfive,stf-vin";
reg = <0x0 0x19800000 0x0 0x10000>,
<0x0 0x19810000 0x0 0x10000>,
<0x0 0x19820000 0x0 0x10000>,
<0x0 0x19830000 0x0 0x10000>,
<0x0 0x19840000 0x0 0x10000>,
<0x0 0x19870000 0x0 0x30000>,
<0x0 0x198a0000 0x0 0x30000>,
<0x0 0x11800000 0x0 0x10000>,
<0x0 0x11840000 0x0 0x10000>,
<0x0 0x11858000 0x0 0x10000>;
reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
"isp0", "isp1", "tclk", "trst", "iopad";
interrupts = <119 109>;
memory-region = <&vin_reserved>;
/*defaule config for imx219 vin&isp*/
format = <SRC_CSI2RX_VIN_ISP>;
frame-width = <800>;
frame-height =<480>;
isp0_enable;
csi-lane = <2>;
csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
csi-clane-swap = /bits/ 8 <0>;
csi-clane-pn-swap = /bits/ 8 <0>;
csi-mipiID = <0>;
csi-width = <1920>;
csi-height = <1080>;
csi-dt = <0x2b>;
};
sfctemp: tmon@124a0000 {
compatible = "starfive,jh7100-temp";
reg = <0x0 0x124a0000 0x0 0x10000>;
#thermal-sensor-cells = <0>;
interrupts = <122>;
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <15000>;
thermal-sensors = <&sfctemp>;
cooling-maps {
};
trips {
cpu_alert0: cpu_alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
otp: otp@11810000 {
compatible = "starfive,fu740-otp";
reg = <0x0 0x11810000 0x0 0x10000>;
fuse-count = <0x200>;
clocks = <&clkgen JH7100_CLK_OTP_APB>;
};
};
};