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riscv: alternative only works on !XIP_KERNEL
commitc80ee64a80
upstream. The alternative mechanism needs runtime code patching, it can't work on XIP_KERNEL. And the errata workarounds are implemented via the alternative mechanism. So add !XIP_KERNEL dependency for alternative and erratas. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Fixes:44c9225729
("RISC-V: enable XIP") Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 3 additions and 2 deletions
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@ -2,6 +2,7 @@ menu "CPU errata selection"
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config RISCV_ERRATA_ALTERNATIVE
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bool "RISC-V alternative scheme"
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depends on !XIP_KERNEL
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default y
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help
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This Kconfig allows the kernel to automatically patch the
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@ -14,8 +14,8 @@ config SOC_SIFIVE
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select CLK_SIFIVE
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select CLK_SIFIVE_PRCI
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select SIFIVE_PLIC
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select RISCV_ERRATA_ALTERNATIVE
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select ERRATA_SIFIVE
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select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL
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select ERRATA_SIFIVE if !XIP_KERNEL
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help
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This enables support for SiFive SoC platform hardware.
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