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drm/nve0/fifo: keep mmu fault interrupts enabled at all times

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-01-09 12:30:43 +10:00
parent e1b6b14ad5
commit 649ec925ae
1 changed files with 16 additions and 1 deletions
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17
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
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@ -753,6 +753,21 @@ nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
nv_mask(priv, 0x002140, 0x80000000, 0x00000000); nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
} }
int
nve0_fifo_fini(struct nouveau_object *object, bool suspend)
{
struct nve0_fifo_priv *priv = (void *)object;
int ret;
ret = nouveau_fifo_fini(&priv->base, suspend);
if (ret)
return ret;
/* allow mmu fault interrupts, even when we're not using fifo */
nv_mask(priv, 0x002140, 0x10000000, 0x10000000);
return 0;
}
int int
nve0_fifo_init(struct nouveau_object *object) nve0_fifo_init(struct nouveau_object *object)
{ {
@ -855,7 +870,7 @@ nve0_fifo_oclass = &(struct nve0_fifo_impl) {
.ctor = nve0_fifo_ctor, .ctor = nve0_fifo_ctor,
.dtor = nve0_fifo_dtor, .dtor = nve0_fifo_dtor,
.init = nve0_fifo_init, .init = nve0_fifo_init,
.fini = _nouveau_fifo_fini, .fini = nve0_fifo_fini,
}, },
.channels = 4096, .channels = 4096,
}.base; }.base;