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drm: bridge: icn6211: Fix HFP_HSW_HBP_HI and HFP_MIN handling
[ Upstream commitc0ff7a649d
] The HFP_HSW_HBP_HI register must be programmed with 2 LSbits of each Horizontal Front Porch/Sync/Back Porch. Currently the driver programs this register to 0, which breaks displays with either value above 255. The HFP_MIN register must be set to the same value as HFP_LI, otherwise there is visible image distortion, usually in the form of missing lines at the bottom of the panel. Fix this by correctly programming the HFP_HSW_HBP_HI and HFP_MIN registers. Acked-by: Maxime Ripard <maxime@cerno.tech> Fixes:ce517f1894
("drm: bridge: Add Chipone ICN6211 MIPI-DSI to RGB bridge") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Robert Foss <robert.foss@linaro.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> To: dri-devel@lists.freedesktop.org Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220331150509.9838-3-marex@denx.de Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 16 additions and 7 deletions
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@ -34,6 +34,9 @@
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#define HSYNC_LI 0x24
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#define HBP_LI 0x25
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#define HFP_HSW_HBP_HI 0x26
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#define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4)
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#define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6)
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#define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8)
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#define VFP 0x27
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#define VSYNC 0x28
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#define VBP 0x29
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@ -165,6 +168,7 @@ static void chipone_enable(struct drm_bridge *bridge)
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{
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struct chipone *icn = bridge_to_chipone(bridge);
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struct drm_display_mode *mode = bridge_to_mode(bridge);
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u16 hfp, hbp, hsync;
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ICN6211_DSI(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
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@ -180,13 +184,18 @@ static void chipone_enable(struct drm_bridge *bridge)
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((mode->hdisplay >> 8) & 0xf) |
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(((mode->vdisplay >> 8) & 0xf) << 4));
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ICN6211_DSI(icn, HFP_LI, mode->hsync_start - mode->hdisplay);
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hfp = mode->hsync_start - mode->hdisplay;
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hsync = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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ICN6211_DSI(icn, HSYNC_LI, mode->hsync_end - mode->hsync_start);
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ICN6211_DSI(icn, HBP_LI, mode->htotal - mode->hsync_end);
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ICN6211_DSI(icn, HFP_HSW_HBP_HI, 0x00);
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ICN6211_DSI(icn, HFP_LI, hfp & 0xff);
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ICN6211_DSI(icn, HSYNC_LI, hsync & 0xff);
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ICN6211_DSI(icn, HBP_LI, hbp & 0xff);
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/* Top two bits of Horizontal Front porch/Sync/Back porch */
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ICN6211_DSI(icn, HFP_HSW_HBP_HI,
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HFP_HSW_HBP_HI_HFP(hfp) |
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HFP_HSW_HBP_HI_HS(hsync) |
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HFP_HSW_HBP_HI_HBP(hbp));
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ICN6211_DSI(icn, VFP, mode->vsync_start - mode->vdisplay);
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@ -196,7 +205,7 @@ static void chipone_enable(struct drm_bridge *bridge)
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/* dsi specific sequence */
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ICN6211_DSI(icn, SYNC_EVENT_DLY, 0x80);
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ICN6211_DSI(icn, HFP_MIN, 0x28);
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ICN6211_DSI(icn, HFP_MIN, hfp & 0xff);
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ICN6211_DSI(icn, MIPI_PD_CK_LANE, 0xa0);
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ICN6211_DSI(icn, PLL_CTRL(12), 0xff);
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ICN6211_DSI(icn, BIST_POL, BIST_POL_DE_POL);
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